24 Commits

Author	SHA1	Message	Date
David Harris	f7b94c12fc	Moved lsuvirtmem muxes into hptw	2022-11-07 11:13:34 -08:00
David Harris	60cfa0d69c	HPTW cleanup	2022-11-04 15:21:09 -07:00
Ross Thompson	51408c620e	Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.	2022-10-23 13:46:50 -05:00
David Harris	ea153e0aad	Removed FStore2 and simplified HPTW	2022-08-22 13:29:54 -07:00
David Harris	fb725a9e0a	Clean up unused signals	2022-05-12 14:49:58 +00:00
David Harris	8066ba45e8	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
David Harris	3519a20ccf	hptw cleanup for synthesis	2022-02-28 05:54:34 +00:00
Ross Thompson	2f711fb642	Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.	2022-02-21 16:54:38 -06:00
Ross Thompson	0c65ea96d8	Cleaned up names in lsuvirtmem.	2022-02-21 16:44:30 -06:00
Ross Thompson	56fc6d0d7c	Minor cleanup of lsu.	2022-02-21 12:46:06 -06:00
David Harris	20a5798f43	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-18 23:08:47 +00:00
David Harris	6a0ffff05d	Removed problematic warning about reaching default state in HPTW	2022-02-18 23:08:40 +00:00
Ross Thompson	6cd9d84e7f	New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.	2022-02-17 17:19:41 -06:00
Ross Thompson	ad237b3ce5	Accidentally cleared dirty bit when setting access bit in hptw.	2022-02-17 16:20:20 -06:00
Ross Thompson	0eec096474	Rough implementation passing regression test with hptw atomic writes to memory.	2022-02-17 14:46:11 -06:00
Ross Thompson	2fc7dc3e57	Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.	2022-02-17 10:04:18 -06:00
Ross Thompson	62f5f1e622	Broken state. address translation not working after changes to hptw to support atomic updates to PT.	2022-02-16 23:37:36 -06:00
David Harris	c23db6a31e	Cleaned warning on HPTW default state	2022-02-16 17:40:13 +00:00
David Harris	5ef8f6bc7e	Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.	2022-02-15 19:20:41 +00:00
David Harris	15fb7fee60	Cleaned up synthesis warnings	2022-02-11 01:15:16 +00:00
David Harris	f7f3882cb8	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
Ross Thompson	4bcabd1a55	Removed unused inputs to hptw.	2022-01-13 11:04:48 -06:00
David Harris	d66f7c841b	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00