Ross Thompson
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50789f9ddd
|
Byte write enables are passing all configs now.
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2022-03-10 17:26:32 -06:00 |
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Ross Thompson
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f7df3a0666
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Progress on the path to getting all configs working with byte write enables.
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2022-03-10 17:02:52 -06:00 |
|
Ross Thompson
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83133f8c47
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Partially working byte write enables. Works for cache, but not dtim or bus only.
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2022-03-10 16:11:39 -06:00 |
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Ross Thompson
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d5f524a15e
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Added byte write enables to cache SRAMs.
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2022-03-10 15:48:31 -06:00 |
|
David Harris
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b1340653cf
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bit write update
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2022-03-09 19:09:20 +00:00 |
|
David Harris
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004853c312
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Refactored SRAM bit write enable
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2022-03-09 17:49:28 +00:00 |
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David Harris
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ba9320d822
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Updated testbench to read expected flags
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2022-03-09 13:58:17 +00:00 |
|
Ross Thompson
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2a8a1cd191
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Minor cleanup to interlockfsm.
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2022-03-08 23:38:58 -06:00 |
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Ross Thompson
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ac9528b450
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-08 18:05:35 -06:00 |
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Ross Thompson
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ed32801cc1
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Comments.
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2022-03-08 18:05:25 -06:00 |
|
Ross Thompson
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534fd70f76
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Marked signals for name changes.
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2022-03-08 17:41:02 -06:00 |
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David Harris
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5d0b9bab6e
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Added more test cases and rounding modes to fma test generator
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2022-03-08 23:29:29 +00:00 |
|
David Harris
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582b943380
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fixed setup.sh merge conflict
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2022-03-08 23:21:06 +00:00 |
|
David Harris
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cfa82efccc
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fma16_testgen.c test cases
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2022-03-08 23:18:18 +00:00 |
|
Ross Thompson
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acd60218b8
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Removed unused signal.
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2022-03-08 16:58:26 -06:00 |
|
Ross Thompson
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cc21414051
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Added parameter to spillsupport.
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2022-03-08 16:38:48 -06:00 |
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Ross Thompson
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60e6c1ffa7
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Moved cacheable signal into cache.
|
2022-03-08 16:34:02 -06:00 |
|
bbracker
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e3303331ef
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change genTrace to dump UART output to file so we can see how far parsing got
|
2022-03-08 09:52:17 -08:00 |
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bbracker
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51e68819c4
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fix up PLIC and UART checkpointing
|
2022-03-07 23:48:47 -08:00 |
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bbracker
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9dbcdca433
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change UART state saving to temporarily modify LCR so that DLAB=0 when reading addresses 0 and 1 so that we get RBR and IER instead of divisor latch registers
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2022-03-07 22:12:08 -08:00 |
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bbracker
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c2ac18b5de
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change testbench-linux.sv to use new shared location of disassembly files
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2022-03-07 20:04:08 -08:00 |
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bbracker
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52bfd65fd3
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change checkpoint generation to integrate GDB scripting more cleanly and save UART and PLIC state
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2022-03-07 17:59:49 -08:00 |
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bbracker
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a93f36824d
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modify debug.sh to not rely on external GDB script
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2022-03-07 11:56:04 -08:00 |
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bbracker
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74ff583f9b
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add debug.sh
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2022-03-07 19:52:19 +00:00 |
|
Shreya Sanghai
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b73f81548f
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removed reminant changes
|
2022-03-07 17:36:05 +00:00 |
|
Shreya Sanghai
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b6b4d0f982
|
undid changes to synth script
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2022-03-07 17:32:08 +00:00 |
|
Shreya Sanghai
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31f17d2bf3
|
modified synth script to take config from outputdir
|
2022-03-07 17:12:43 +00:00 |
|
Shreya Sanghai
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4d8e0ecf29
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updated makefile to speed up synth
|
2022-03-07 00:09:18 +00:00 |
|
Shreya Sanghai
|
e4145d32ab
|
modified makefile
|
2022-03-07 00:09:18 +00:00 |
|
bbracker
|
01eeab2131
|
update checkpointSweep in accordance to having removed trace parsing feature
|
2022-03-06 14:55:51 -08:00 |
|
bbracker
|
c432e2175e
|
remove vestigial silencePipe mechanism
|
2022-03-06 14:54:35 -08:00 |
|
bbracker
|
ca6bb7c2d2
|
needed to initialize checkpoint directory
|
2022-03-06 14:51:25 -08:00 |
|
bbracker
|
6b1b471ca6
|
no longer use cythonization on python parser scripts because its a little complicated and has marginal benefit
|
2022-03-06 14:40:26 -08:00 |
|
bbracker
|
2e6fa01b9b
|
give genCheckpoint the same de-sudo'ing treatement
|
2022-03-06 14:37:12 -08:00 |
|
bbracker
|
675e112950
|
better to use $tvDir variable rather than abs path
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2022-03-06 14:33:53 -08:00 |
|
bbracker
|
8720604bfc
|
replace sudo's with suggestions in genRecording.sh
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2022-03-06 14:31:55 -08:00 |
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bbracker
|
3e4ce15ea4
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replace sudo's in genTrace.sh with suggested commands
|
2022-03-06 14:24:50 -08:00 |
|
bbracker
|
3e1f4decf1
|
small bugfix to suggested sudo commands for linux testvectors
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2022-03-06 14:16:23 -08:00 |
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bbracker
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228f693f13
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remove checkpoint trace generation since that requires qemu hacking and because we are able to generate the whole trace on VLSI
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2022-03-06 14:04:30 -08:00 |
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bbracker
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12dd1fb8e3
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add path to Modelsim on vlsi
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2022-03-06 13:55:19 -08:00 |
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bbracker
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f86e76a4b1
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recommend sudo commands without automatically executing them in genInitMem.sh
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2022-03-06 13:30:19 -08:00 |
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bbracker
|
a0d0742227
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change from clang to gcc when compiling testvector-generation executables
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2022-03-06 13:18:53 -08:00 |
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bbracker
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e2d2dbad10
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generate $WALLY in a way that works for bash and zsh
|
2022-03-06 13:12:20 -08:00 |
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bbracker
|
3601cc54ab
|
Revert "fix "dirname: missing operand" bug from setup.sh"
This reverts commit 34c460b451 .
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2022-03-06 12:48:53 -08:00 |
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David Harris
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aebb677f7a
|
Restored setup.sh to use . Working for David. Not sure what is happening for Ben - are you on Bash?
|
2022-03-06 13:39:53 +00:00 |
|
David Harris
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e757ed1162
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Fixed merge of fpcalc
|
2022-03-06 13:32:13 +00:00 |
|
David Harris
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d2282d5e87
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Checked in fma16_template.v
|
2022-03-06 13:29:35 +00:00 |
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bbracker
|
94124cb108
|
add extractFunctionRadix step to buildroot Makefile
|
2022-03-05 19:02:07 -08:00 |
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bbracker
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9f7a434b20
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change genInitMem.sh to check for sufficient directory privileges rather than invoke sudo
|
2022-03-05 18:04:00 -08:00 |
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bbracker
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ddae5f6518
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remove linux-testgen dir because it is now completely obsolete
|
2022-03-05 17:26:30 -08:00 |
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