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Author SHA1 Message Date
David Harris
0c57b61ace Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-20 21:09:20 -08:00
David Harris
001c39d8eb Fixing paths in wally-setup.sh 2021-12-20 21:08:34 -08:00
Ross Thompson
59252208a8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-20 21:26:48 -06:00
Ross Thompson
47638cdccf Looks like rdtime was accidentally replaced with rrame from a find and replace. 2021-12-20 21:26:38 -06:00
David Harris
8072ed242c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-21 02:35:45 +00:00
David Harris
434f49c03e Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead 2021-12-21 02:35:41 +00:00
Ross Thompson
d830721a11 Fixed Type 5b interaction between dcache and hptw. 
This is a load concurrent with ITLBMiss.
 2021-12-20 18:33:31 -06:00
Ross Thompson
6aff6b0fa3 Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM. 2021-12-20 10:03:56 -06:00
Ross Thompson
53736096a6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-20 10:03:19 -06:00
Ross Thompson
b261b18aa8 More signal name cleanup in LSU. 2021-12-19 22:47:48 -06:00
Ross Thompson
533c2f3556 Remove verbosity from lsu state machine. 2021-12-19 22:41:34 -06:00
Ross Thompson
82dd41a0fd Rename of SelPTW to SelHPTW. 2021-12-19 22:24:07 -06:00
Ross Thompson
9c2fc30507 Signal renames. 2021-12-19 22:21:03 -06:00
Ross Thompson
2f5de7eb82 Hardware reductions in the lsu. 2021-12-19 22:00:28 -06:00
Ross Thompson
035ce99938 Removed HPTWStall. Not needed as InterlockStall from the LSU provides the equivalent. 2021-12-19 21:36:54 -06:00
Ross Thompson
30770db4ac Removed lsuArb and placed remaining logic in lsu.sv. 
Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
 2021-12-19 21:34:40 -06:00
Ross Thompson
019e300a14 Added file showing how to compile riscv toolchain for different extension combinations. 2021-12-19 20:31:55 -06:00
Ross Thompson
db76878581 Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card. 
mv qemu patches to tests directory.
 2021-12-19 20:11:32 -06:00
David Harris
193885c958 Moved generate of conditional units to hart 2021-12-19 17:03:57 -08:00
David Harris
1196e5c191 Moved generate statements for optional units into wallypipelinedhart 2021-12-19 16:53:41 -08:00
Ross Thompson
7b2f5440a5 Changes to buildroot to support MemAdrM to IEUAdrM name changes. 2021-12-19 18:24:40 -06:00
Ross Thompson
aeb8c94df1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-19 18:16:49 -06:00
Ross Thompson
cef4b6399d Switched to using an always block for lsu stall logic. This avoids the problematic x propagation. 2021-12-19 18:16:08 -06:00
Ross Thompson
814bcec7b7 Implemented what I think is the last required change for the lsu state machine. 2021-12-19 17:57:12 -06:00
Ross Thompson
54fd8678b0 Created hack to get around imperas64mmu unknown (value = x) bug. 2021-12-19 17:53:13 -06:00
Ross Thompson
13f0e9bafa Fixed bug where icache did not replay PCF on itlb miss. 2021-12-19 17:01:13 -06:00
Ross Thompson
04d0b85f96 Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass. 2021-12-19 16:12:31 -06:00
David Harris
5e1c3e322b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-19 13:53:53 -08:00
David Harris
691c1c0dd0 ALUControl cleanup 2021-12-19 13:53:45 -08:00
Katherine Parry
ece9e9df84 fixed some small errors in FMA 2021-12-19 13:51:46 -08:00
Ross Thompson
202203904c Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm. 2021-12-19 15:10:33 -06:00
Ross Thompson
9adcf86a40 Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage. 
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
 2021-12-19 14:57:42 -06:00
Ross Thompson
0257c08641 Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache. 2021-12-19 14:00:30 -06:00
Ross Thompson
620f4a58d4 Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states. 2021-12-19 13:55:57 -06:00
Ross Thompson
fdf493bd47 minro change. comments about needed changes in dcache. 2021-12-19 13:53:02 -06:00
David Harris
c04c56dae1 Renamed zero to eq in flag generation 2021-12-19 11:49:15 -08:00
David Harris
e5d2d7a3fd Controller fix 2021-12-18 22:08:23 -08:00
David Harris
8a597390e0 Renamed RD1D to R1D, etc. 2021-12-18 21:26:00 -08:00
David Harris
7fb4213751 Simplified shifter right input 2021-12-18 10:25:40 -08:00
Ross Thompson
f601b3ae53 Merge branch 'tlb_fixes' into main 2021-12-18 12:24:17 -06:00
David Harris
d97d34ee32 Simplified Shifter Right input 2021-12-18 10:21:17 -08:00
David Harris
852c521328 Shared ALU mux input for shifts 2021-12-18 10:08:52 -08:00
David Harris
a7d7f852a6 Factored out common parts of shifter 2021-12-18 10:01:12 -08:00
David Harris
7868c0da55 Cleaning shifter 2021-12-18 09:43:09 -08:00
David Harris
b453454b24 Moved W64 truncation after result mux 2021-12-18 09:27:25 -08:00
David Harris
2a5a7eff82 Forwarding logic factoring 2021-12-18 05:40:38 -08:00
David Harris
1212e21eba Simplified FWriteInt interfaces by merging into RegWrite 2021-12-18 05:36:32 -08:00
David Harris
da1df17fbb Do File cleanups 2021-12-17 17:45:26 -08:00
Ross Thompson
2f86e84843 Merge remote-tracking branch 'origin/tlb_fixes' into main 2021-12-17 14:40:29 -06:00
Ross Thompson
79ec4161b6 Added more debugging code for FPGA. 2021-12-17 14:40:25 -06:00