53 Commits

Author	SHA1	Message	Date
David Harris	29ad38fb9e	Added Physical Address and Size to PMA Checker/MMU	2021-06-21 01:27:02 -04:00
David Harris	aef408af58	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
David Harris	a3f3533cce	Changed physical addresses to PA_BITS in size in MMU and TLB	2021-06-18 09:11:31 -04:00
David Harris	cc78504ae4	Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX	2021-06-18 08:13:15 -04:00
David Harris	72d8d34e3c	allow all size memory access in CLINT; added underscore to peripheral address symbols	2021-06-18 08:05:50 -04:00
David Harris	8357b14957	Further cleaning of PMA checker	2021-06-17 22:27:39 -04:00
David Harris	91a13999a9	Added SUPPORTED to each peripheral in each config file	2021-06-17 21:36:32 -04:00
David Harris	5e7ed4bd88	added inputs to pmaadrdec	2021-06-17 18:54:39 -04:00
David Harris	09c5e27853	Started simplifying PMA checker	2021-06-17 16:28:06 -04:00
David Harris	9dd3857c26	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
David Harris	9a17556de4	Start to parameterize number of PMP Entries	2021-06-08 15:29:22 -04:00
David Harris	cfe5c27946	Resized BOOT TIM to 1 KB	2021-06-08 14:04:32 -04:00
Kip Macsai-Goren	be99c18002	making mmu branch line up with main	2021-06-08 13:59:03 -04:00
Kip Macsai-Goren	41ceb20296	some cleanup of signals, not done yet	2021-06-08 13:39:32 -04:00
Kip Macsai-Goren	e044f72e59	remove redundant decodes, fixed mmu logic ins/outs	2021-06-07 19:23:30 -04:00
Kip Macsai-Goren	146ed95bdb	got rid of some underscores in filenames, modules	2021-06-07 18:54:05 -04:00
Kip Macsai-Goren	46b2b19792	implemented simpler page mixers, cleaned up a bit	2021-06-07 18:32:34 -04:00
Kip Macsai-Goren	55d50f5607	began updating cam line to reduce muxes, confusion	2021-06-07 17:03:31 -04:00
Kip Macsai-Goren	1377680270	regression working partially done page mask	2021-06-07 17:02:31 -04:00
David Harris	c3d21967f8	Simplified superpage matching	2021-06-07 16:11:28 -04:00
David Harris	b37bcc8e38	Continued merge	2021-06-07 12:49:47 -04:00
David Harris	1e67db2f0c	Second attept to commit refactoring config files	2021-06-07 12:37:46 -04:00
David Harris	95cc70295b	Merge difficulties	2021-06-07 09:50:23 -04:00
David Harris	8bbabb683d	Refactored configuration files and renamed testbench-busybear to testbench-linux	2021-06-07 09:46:52 -04:00
Kip Macsai-Goren	d69501c4fa	Cleaned up some unused signals	2021-06-04 21:04:19 -04:00
Kip Macsai-Goren	b99b5f8e0e	moved privilege dfinitions into wally-constants, upgraded relevant includes	2021-06-04 17:55:07 -04:00
Kip Macsai-Goren	7e41b17e65	restructured so that pma/pmp are a part of mmu	2021-06-04 17:05:07 -04:00
David Harris	b836679ae1	Started MMU	2021-06-04 11:59:14 -04:00
Kip Macsai-Goren	f7deda0514	implemented Sv48.	2021-06-01 17:50:37 -04:00
Kip Macsai-Goren	529226ac8d	made priority encoder parameterizable	2021-05-28 18:09:28 -04:00
Thomas Fleming	fda439b51e	Fix comment	2021-05-14 08:06:07 -04:00
Thomas Fleming	980c00fa64	Clean up MMU code	2021-05-14 07:12:32 -04:00
bbracker	535046e494	small synthesis fixes	2021-05-04 15:21:01 -04:00
Thomas Fleming	d22f0f9d63	Refactor tlb_ram to use flop primitives	2021-04-22 01:52:43 -04:00
Thomas Fleming	70c801331a	Implement virtual memory protection	2021-04-21 19:58:36 -04:00
Thomas Fleming	e8770e3eac	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/mmu/priority_encoder.sv	2021-04-15 16:20:43 -04:00
Thomas Fleming	e838f0bb3d	Change priority encoder to avoid extra assignment	2021-04-15 16:17:35 -04:00
Teo Ene	cefc8ea22b	Temporary change to mmu/priority_encoder.sv ... Necessary to get synth working Original HDL is still there, just commented out	2021-04-15 13:37:12 -05:00
Thomas Fleming	bb2d433971	Fix mmu lint errors	2021-04-13 19:19:58 -04:00
Thomas Fleming	ae888b5705	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/ebu/pagetablewalker.sv	2021-04-13 13:42:03 -04:00
Thomas Fleming	08a84048b6	Add lru algorithm to TLB	2021-04-13 13:37:24 -04:00
Teo Ene	0bffac2c74	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
Thomas Fleming	bd310a55af	Refactor TLB into multiple files	2021-04-08 03:24:10 -04:00
Thomas Fleming	b3795cef2e	Provide attribution link for priority encoder	2021-04-08 03:05:06 -04:00
Thomas Fleming	e807f5d771	Implement support for superpages	2021-04-08 02:44:59 -04:00
Thomas Fleming	e04ad8f304	Fix extraneous page fault stall	2021-04-03 21:28:24 -04:00
Thomas Fleming	f9bf2fbc01	Implement sfence.vma and fix tlb writing	2021-04-01 15:55:05 -04:00
Thomas Fleming	9388a9f28a	Disable 'always-on' virtual memory	2021-03-30 22:49:47 -04:00
Thomas Fleming	4b2765f8e2	Complete basic page table walker	2021-03-30 22:19:27 -04:00
Thomas Fleming	062c4d40da	Connect tlb, pagetablewalker, and memory	2021-03-18 14:35:46 -04:00