David Harris
aad1d3d7dd
Moved writeback pipeline registers from datapth into DMEM and CSR
2021-02-02 13:02:31 -05:00
Jarred Allen
5090537f3c
Fix intermittent errors caused by weird library stuff
2021-02-02 11:20:09 -05:00
Jarred Allen
8dcb4b2d57
Add the regression logs and new regression byproducts to the gitignore
2021-02-02 10:43:41 -05:00
Noah Boorstin
8d53e36bbc
Busybear: start checking CSRs
...
scounteren and mcounteren are currenly manually deleted from the CSRs list
(see slack channl #linux-bringup)
and 3 of the CSRs referenced are skipped because of weird locations for them
oh and this doesn't check their initial state, just their changing. This could be a problem
2021-02-02 06:06:03 +00:00
David Harris
9d7e242596
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
Jarred Allen
2b75e38239
Fix issues in parallel regression testing
2021-02-01 23:29:03 -05:00
Noah Boorstin
c634b2f81e
busybear: start adding CSR checking
...
@kaveh is there a less verbose way to do this?
2021-02-01 22:08:51 -05:00
Brett Mathis
94de3e9fb2
OSU FPU IP initial commit
2021-02-01 19:33:43 -06:00
Noah Boorstin
ff88214730
busybear: change register file checking to only store register changed
...
this should make parsedRegs.txt much smaller
2021-02-02 01:27:43 +00:00
Noah Boorstin
416b3fc96c
Add PCW checking
...
for now, doesn't check InstrW because it fails on compressed instructions
2021-02-01 23:57:33 +00:00
David Harris
056b147b13
Renamed DCU to DMEM
2021-02-01 18:52:22 -05:00
Jarred Allen
84801213d6
Parallelize regression-wally.p
2021-02-01 15:40:27 -05:00
Noah Boorstin
a432d607ce
busybear: print warning when NOPing out instructions
2021-02-01 19:44:56 +00:00
Noah Boorstin
b7f63c1dc7
busybear: NOP out floating point instructions for now
...
Why does linux even try to do float stuff doing booting??
also, now runs the first 100k instructions!
2021-01-30 19:52:47 +00:00
Noah Boorstin
4358f086be
update busybear testbench to conform to new structure
...
aaaaaaaaaaaaaaaaaahhhh so many changes
also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
2021-01-30 19:19:00 +00:00
David Harris
396cea1ea7
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
David Harris
fc1fb94217
Working on reading instruction from TIM
2021-01-30 01:57:51 -05:00
David Harris
61fd7c4499
Adding stalls for memory delays
2021-01-30 01:43:49 -05:00
David Harris
9c81278f28
Added HCLK and HRESETn
2021-01-30 00:56:12 -05:00
David Harris
a357f2a0e7
Connected AHB bus to Uncore
2021-01-29 23:43:48 -05:00
David Harris
73a584b223
Added SATP, PMPCFG0-3, PMPADDR0 CSRs for Linux team
2021-01-29 18:06:36 -05:00
David Harris
e700e404c9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 17:29:01 -05:00
David Harris
9a51bb27c3
Implemented adrdec for uncore
2021-01-29 17:28:53 -05:00
Teo Ene
9eafdbe349
- Removed latch on CSRCReadValM in csrc.sv
...
- Changed top level to wallypipelinedhart
2021-01-29 15:56:51 -06:00
Teo Ene
8679e9aae3
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-01-29 15:04:51 -06:00
Teo Ene
94b35ac47c
Synth automatically globs all available verilog files now, instead of requiring manual file listing
2021-01-29 15:04:43 -06:00
David Harris
8d4f5277d2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 15:38:01 -05:00
David Harris
dc2443c55b
Moving data memory to uncore
2021-01-29 15:37:51 -05:00
Teo Ene
3d02d6f09f
Added AHBW to rv32ic config file as well
2021-01-29 12:29:08 -06:00
Noah Boorstin
194d5b55ab
update busybear testbench to conform to new structure
2021-01-29 17:46:50 +00:00
David Harris
a94c09cad8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 01:07:22 -05:00
David Harris
ed3cb83c10
Added ahblite bus interface unit
2021-01-29 01:07:17 -05:00
Noah Boorstin
dabb026104
busybear: lie about MISA to match OVP's MISA
2021-01-29 00:58:56 -05:00
Noah Boorstin
8ab5879af5
busybear testbench: test on first 100k instrs
...
currently gets about 47k instrs correctly
also fix gdb parsing to avoid accidently matching on function names
2021-01-29 00:14:23 -05:00
David Harris
618c6e4813
Renamed modules in privileged unit
2021-01-28 23:21:12 -05:00
David Harris
fd2f854a69
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-28 21:40:57 -05:00
David Harris
05b755958f
Hint to optimize ifu
2021-01-28 21:40:48 -05:00
Noah Boorstin
619dec1490
busybear: simulate first 10k instructions
...
I know we need to add CSR checking sometime soon
Also I'm a bit sketpical this is all working properly, and that no new bugs
were uncovered from 1k instrs to 10k instrs
2021-01-28 19:44:58 -05:00
Noah Boorstin
4f84bd3c8f
busybear: fix misaligned writing checking
2021-01-28 19:35:09 -05:00
Noah Boorstin
beb93e2508
busybear: add more test instructions
...
currently testing first 1k instrs
2021-01-28 16:41:37 -05:00
Noah Boorstin
287cf4e5a6
oops forgot to add C.BEQZ, C.BNEZ checks to busybear testbench
2021-01-28 16:35:12 -05:00
Noah Boorstin
91e9defd0a
more of the same fixes
2021-01-28 16:26:15 -05:00
Noah Boorstin
623d9feeab
more misaligned read fixing
...
I'm getting fairly concerned about this, I feel like
this should only work if the memory ignores the lower 3 or 4 bits of the adr
2021-01-28 16:14:35 -05:00
David Harris
12c6006f07
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-28 15:44:14 -05:00
David Harris
fe0876027f
Fixed floating signals in clint and ieu
2021-01-28 15:44:05 -05:00
Noah Boorstin
405c9d90b5
busybear testbench: understand bytemask for writes
2021-01-28 15:42:47 -05:00
Noah Boorstin
7a3f29b260
Make gdb output parser understand other varients of load/store
2021-01-28 15:35:41 -05:00
David Harris
ad5d4793b6
Fixed c.jr instruction improperly writing ra
2021-01-28 15:18:23 -05:00
Noah Boorstin
a4bac85ece
busybear: ret is only 1 word
2021-01-28 14:47:40 -05:00
Noah Boorstin
0befdfacec
add speculative exception for compressed instructions
2021-01-28 14:40:35 -05:00
