12 Commits

Author	SHA1	Message	Date
David Harris	0ede295e88	Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields	2022-04-25 14:49:00 +00:00
David Harris	851d5e8c5e	Added MTINST hardwired to 0, and added timeout of U-mode WFI	2022-04-24 20:00:02 +00:00
Ross Thompson	0340c0fd44	Added wave config ... added new signals to ILA.	2022-04-01 12:44:14 -05:00
bbracker	54b9745a75	big interrupts refactor	2022-03-30 13:22:41 -07:00
David Harris	d8170e9dd3	Mostly removed N_SUPPORTED	2022-02-15 19:50:44 +00:00
David Harris	c12407ba6a	Removed Busybear dependencies	2022-02-02 20:28:21 +00:00
Ross Thompson	ec44774c77	Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv	2022-01-20 16:39:54 -06:00
Ross Thompson	5cf686429d	Merged in the debug ila updates.	2022-01-18 17:29:21 -06:00
Ross Thompson	fdc17f5017	Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.	2022-01-18 17:19:33 -06:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	d66f7c841b	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00