104 Commits

Author	SHA1	Message	Date
David Harris	27588af00e	Clean up sqrt initialization mux	2022-12-30 06:55:20 -08:00
David Harris	802c440254	Reduced size of preproc right shift	2022-12-30 06:47:40 -08:00
David Harris	d2273e7037	fdivsqrtpreproc shift simplification	2022-12-30 06:45:51 -08:00
David Harris	18f19ce44d	fdiv cleanup, reduce number of rv32f fma_b15 tests being run to speed up regression	2022-12-30 06:40:25 -08:00
David Harris	0ecbb45b78	Fixed register timing failure on SpecialCaseM in fdivsqrt	2022-12-29 21:09:23 -08:00
David Harris	963185fb22	Clean up names and comments in divsqrt	2022-12-29 08:02:44 -08:00
David Harris	103c4b8324	Factored out hardware unique to RV64 and to IDIV	2022-12-29 07:36:26 -08:00
David Harris	a9d7aa568a	fdivsqrtfsm conditional on IDIV (fixed typo)	2022-12-27 22:16:48 -08:00
David Harris	5b7e814670	fdivsqrtfsm conditional on IDIV	2022-12-27 22:15:45 -08:00
David Harris	4648fbee76	fdivsqrtfsm conditional on IDIV	2022-12-27 22:14:09 -08:00
Cedar Turek	42d2ca1556	idiv passing radix 2, four copies	2022-12-27 22:11:18 -08:00
David Harris	f16a15e66f	Moved IDIV in fdivsqrtfms into generate block	2022-12-27 22:04:50 -08:00
David Harris	3975fd5ed8	Moved IDIV for postproc into generate block	2022-12-27 22:02:14 -08:00
David Harris	62c01d865a	Moved IDIV_ON_FP into conditional block in fdivsqrtpreproc	2022-12-27 21:53:00 -08:00
Cedar Turek	00073155c5	Fixed cycles for multiple iterations. 2-copies radix 2 passing regression.	2022-12-27 21:34:27 -08:00
David Harris	20787964c9	Renamed muldiv to mdu	2022-12-27 19:57:10 -08:00
David Harris	9544051c1e	Removed MDUE from unnecessary places in fdivsqrt	2022-12-27 10:42:40 -08:00
David Harris	c903f8b8b2	fdiv typo	2022-12-27 10:30:42 -08:00
David Harris	ed26850439	Made SqrtE only true on square root so gating with ~MDUE can be removed)	2022-12-27 10:27:07 -08:00
David Harris	f5cc23cae9	Check for non-negative W in int sign handling	2022-12-27 06:35:17 -08:00
Cedar Turek	d41b07aa85	fpu idiv working on all configs with 1 copy of radix 2!	2022-12-26 23:18:28 -08:00
Cedar Turek	21b2ea9666	fpu passing idiv tests on rv32gc 1 copy of radix 2!	2022-12-26 21:47:56 -08:00
Cedar Turek	6977b7ceac	took out otfc swap. updated postprocessing quotient/remainder logic for int div.	2022-12-26 21:03:56 -08:00
David Harris	add381a09e	Fixed early termination for square root	2022-12-26 08:54:57 -08:00
David Harris	71f214df20	Moved fdivsqrtexpcalc to its own file	2022-12-26 08:45:43 -08:00
cturek	ba3aca413c	Added A Sign register. Fixed postprocessing logic for postinc and rem calculation.	2022-12-24 06:46:52 +00:00
David Harris	98ecd9c77d	Commented out fdiv early termination - broke fsqrt test	2022-12-23 00:58:55 -08:00
David Harris	04dd3e5144	Fixed early termination on fdivsqrt	2022-12-23 00:53:55 -08:00
David Harris	fe5b9081d9	Removed unused signals from FPU	2022-12-23 00:18:39 -08:00
David Harris	93bb8036be	Revert to 98b824	2022-12-22 23:58:14 -08:00
David Harris	a185f563f2	Clean up unused FPU signals	2022-12-22 23:53:09 -08:00
David Harris	74979cdc82	FDIV merge	2022-12-22 23:03:03 -08:00
David Harris	51b92285d3	Removed unused signals in FPU and CSR	2022-12-22 22:59:05 -08:00
cturek	04bc787647	Added negative-result int diviison support in U and UM registers. 13 tests pass!	2022-12-22 16:25:37 +00:00
cturek	1712e69c73	Moved swap from qslc to otfc	2022-12-22 15:44:50 +00:00
cturek	c7d0c8823f	Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc.	2022-12-22 05:44:55 +00:00
cturek	c405dcf0cb	worked out some bugs with int div cycles	2022-12-22 02:22:01 +00:00
cturek	e441f90b32	Renamed signals to E and M stages, forwarded preprocessed n to fsm	2022-12-22 00:43:27 +00:00
cturek	14d9118802	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-12-21 19:35:57 +00:00
cturek	6761101645	fixed normshift calculations	2022-12-21 19:35:47 +00:00
David Harris	9133b3a7a4	FPU remove unused signals	2022-12-20 14:43:30 -08:00
Alessandro Maiuolo	13c9f2e4a5	Added NumZeroE, AZeroM, and BZeroM	2022-12-18 20:02:40 -08:00
Alessandro Maiuolo	3bcb42adb6	fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)	2022-12-18 19:04:36 -08:00
cturek	0ceecd9961	Added integer support for initC	2022-12-16 19:02:11 +00:00
cturek	9340a5eb49	Added mux for integer special case, renamed signals to match pipelined stage	2022-12-16 18:43:49 +00:00
David Harris	a285f289a6	Disabled starting FPU divider when IDIV_ON_FPU = 0	2022-12-16 06:35:29 -08:00
cturek	9f1aa7ad19	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-12-16 03:41:39 +00:00
David Harris	a8126458f6	Refactored stalls and flushes, including FDIV flush with FlushE	2022-12-15 10:56:18 -08:00
David Harris	643a2e7cf9	Use FPU divider for integer division when F is supported	2022-12-14 17:03:13 -08:00
cturek	482caec42d	Fixed BZero and initU/initUM muxes	2022-12-14 16:44:46 +00:00