David Harris
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72c1cc33f5
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Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
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2021-09-15 13:14:00 -04:00 |
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Ross Thompson
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3b12235954
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Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches.
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2021-09-11 15:40:27 -05:00 |
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Katherine Parry
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7607adc951
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FMA cleanup
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2021-08-28 10:53:35 -04:00 |
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Katherine Parry
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567260751a
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move some FPU select muxs to execute stage
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2021-08-13 14:41:22 -04:00 |
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Katherine Parry
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21555c392f
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LZA added to FMA and attemting a merged FMA and adder in synthesis
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2021-08-10 13:57:16 -04:00 |
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Ross Thompson
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d430659983
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fixed the read timer issue but we still have problems with interrupts and i/o devices.
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2021-08-06 10:16:06 -05:00 |
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Katherine Parry
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67ab0b165c
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fpu cleanup
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2021-07-24 14:59:57 -04:00 |
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David Harris
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c117356432
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Parameterized I$/D$ configurations and added sanity check assertions in testbench
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2021-07-20 08:57:13 -04:00 |
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David Harris
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b2f7952b3d
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Added cache configuration to config files
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2021-07-19 18:19:46 -04:00 |
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Katherine Parry
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701ea38964
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Fixed lint warning
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2021-07-14 21:24:48 -04:00 |
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Katherine Parry
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acdd2e4504
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Fixed writting MStatus FS bits
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2021-07-13 13:20:30 -04:00 |
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Katherine Parry
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0cc07fda1b
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Almost all convert instructions pass Imperas tests
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2021-07-11 18:06:33 -04:00 |
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David Harris
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a390736f26
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Don't generate HPTW when MEM_VIRTMEM=0
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2021-07-05 23:35:44 -04:00 |
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David Harris
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6b9cfe90d8
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Added ASID & Global PTE handling to TLB CAM
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2021-07-04 17:52:00 -04:00 |
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David Harris
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c897bef8cd
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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bbracker
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83a1f29c37
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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
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2021-06-20 22:38:25 -04:00 |
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Katherine Parry
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26bad083ad
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all rv64f instructions except convert, divide, square root, and FLD pass
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2021-06-20 20:24:09 -04:00 |
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David Harris
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72d8d34e3c
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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91a13999a9
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Added SUPPORTED to each peripheral in each config file
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2021-06-17 21:36:32 -04:00 |
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Katherine Parry
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920ff984ca
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Updated FMA
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2021-06-14 13:42:53 -04:00 |
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David Harris
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e231fc6b00
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More verilator fixes, but bpred is broken
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2021-06-09 21:03:03 -04:00 |
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Kip Macsai-Goren
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fcb9b1f0e1
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working version with new mmu comments, old boottim values
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2021-06-08 15:20:25 -04:00 |
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David Harris
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cfe5c27946
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Resized BOOT TIM to 1 KB
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2021-06-08 14:04:32 -04:00 |
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David Harris
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b37bcc8e38
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Continued merge
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2021-06-07 12:49:47 -04:00 |
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David Harris
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1e67db2f0c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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David Harris
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95cc70295b
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Merge difficulties
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2021-06-07 09:50:23 -04:00 |
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David Harris
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8bbabb683d
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Refactored configuration files and renamed testbench-busybear to testbench-linux
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2021-06-07 09:46:52 -04:00 |
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Kip Macsai-Goren
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b99b5f8e0e
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moved privilege dfinitions into wally-constants, upgraded relevant includes
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2021-06-04 17:55:07 -04:00 |
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David Harris
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b836679ae1
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Started MMU
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2021-06-04 11:59:14 -04:00 |
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David Harris
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a61411995a
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moved shared constants to a shared directory
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2021-06-03 22:41:30 -04:00 |
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Kip Macsai-Goren
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06cf3a8403
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Edited and added constants to support SV48
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2021-06-01 17:49:45 -04:00 |
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James E. Stine
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474d479280
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Update to rv64icfd wally-config to run through FP tests
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2021-05-21 09:22:17 -05:00 |
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James E. Stine
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f407bee5ae
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Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
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2021-05-18 13:48:44 -05:00 |
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Ross Thompson
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14a69c1d06
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Added the ability to exclude branch predictor.
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2021-04-26 14:27:42 -05:00 |
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Noah Boorstin
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5902637632
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buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
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2021-04-17 14:44:32 -04:00 |
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Domenico Ottolia
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a149f2f3d8
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Add support for vectored interrupts
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2021-04-15 19:13:42 -04:00 |
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Shreya Sanghai
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75caa65df1
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Cherry Pick merge of Shreya's localhistory predictor changes into main.
fixed minor bugs in localHistory
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2021-04-15 09:04:36 -05:00 |
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Thomas Fleming
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e807f5d771
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Implement support for superpages
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2021-04-08 02:44:59 -04:00 |
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Thomas Fleming
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4b2765f8e2
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Complete basic page table walker
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2021-03-30 22:19:27 -04:00 |
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bbracker
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eea7e2e47e
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first pass at PLIC interface
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2021-03-22 10:14:21 -04:00 |
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Shreya Sanghai
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dfc86539cc
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Merge branch 'gshare' into main
Conflicts:
wally-pipelined/regression/wave.do
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2021-03-18 17:25:48 -04:00 |
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Ross Thompson
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9386e6a524
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Switched to gshare from global history.
Fixed a few minor bugs.
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2021-03-18 16:05:59 -05:00 |
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Noah Boorstin
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847bf0b9a6
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change ifndef to generate/if
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2021-03-18 12:50:19 -04:00 |
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Noah Boorstin
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fa1407f6e3
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everyone gets a bootram
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2021-03-18 12:35:37 -04:00 |
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Shreya Sanghai
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d9b1e7d67f
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added gshare and global history predictor
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2021-03-16 17:03:01 -04:00 |
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Shreya Sanghai
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a79e26f9d8
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added global history branch predictor
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2021-03-16 16:06:40 -04:00 |
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Shreya Sanghai
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518618ad38
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Merge branch 'counters' into main
added a configurable number of performance counters
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2021-03-16 11:01:30 -04:00 |
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Ross Thompson
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8e51935082
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Converted branch predictor preloads to use system verilog rather than modelsim's load command.
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2021-03-15 12:39:44 -05:00 |
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Thomas Fleming
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e57b6cf18c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
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2021-03-11 00:15:58 -05:00 |
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Ross Thompson
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9a93193d6a
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Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
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2021-03-05 15:23:53 -06:00 |
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