Github_Repos/cvw
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1201 Commits

Author SHA1 Message Date
David Harris
05aa18fe14 Cleaned up fcvt selection control to IEU and FPUIllegalInst signals 2022-08-23 12:17:19 -07:00
David Harris
d19fc99bf0 Simplify IEU-FP datapath 2022-08-23 11:16:36 -07:00
David Harris
f72d07adce Improved illegal instruction checking in FPU 2022-08-23 11:08:02 -07:00
David Harris
c61dba6192 Fixed LSU typos 2022-08-23 10:23:08 -07:00
David Harris
2a1bd53663 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-23 10:14:59 -07:00
David Harris
029aecabf7 typo in srtfsm 2022-08-23 10:14:54 -07:00
Katherine Parry
fe0c6afe58 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-23 16:36:32 +00:00
Katherine Parry
4e33ead413 renamed rounding bits to L,G,R,S and fixed lint warning 2022-08-23 16:36:20 +00:00
Ross Thompson
8d4301e2f6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-23 11:15:04 -05:00
Ross Thompson
20ba6fd19c Reversed order of supported sized in adrdecs. 2022-08-23 11:14:53 -05:00
Ross Thompson
5efec3b1f3 Replaced FPU data replicaiton on WriteData bus with 0 extention. 2022-08-23 10:46:03 -05:00
Ross Thompson
aa5cbab0d8 Replaced LSU data replication with 0 extention. 2022-08-23 10:43:47 -05:00
Ross Thompson
3b07584403 Updated the names of the *WriteDataM inside the LSU to more meaningful names. 
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
 2022-08-23 10:34:39 -05:00
David Harris
7fcc852687 Q depends on D 2022-08-23 08:29:59 -07:00
David Harris
e714b75888 LSU minor edits 2022-08-23 07:35:47 -07:00
David Harris
16a92eaf10 Updated testbench assertions. 2022-08-23 07:23:24 -07:00
David Harris
3c91df95d9 Named HTRANS states in busfsm 2022-08-22 13:56:46 -07:00
David Harris
6cfbf95d98 Renamed signals for LSU - FPU interface 2022-08-22 13:47:56 -07:00
David Harris
c789b5789c renamed GrantData to LSUGrant 2022-08-22 13:47:19 -07:00
David Harris
0e489443f2 Finished FPU-LSU interface cleanup 2022-08-22 13:43:04 -07:00
David Harris
ea153e0aad Removed FStore2 and simplified HPTW 2022-08-22 13:29:54 -07:00
David Harris
8444eca57c Simplified FPU-LSU interface to skip IEU 2022-08-22 13:29:20 -07:00
David Harris
774cddf33c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-22 13:28:54 -07:00
David Harris
d556adde16 Simplified FPU-LSU interface to skip IEU 2022-08-22 13:28:51 -07:00
Katherine Parry
a9be193a35 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-22 17:16:25 +00:00
Katherine Parry
36be692c0b sqrt passes - lint warnings remain 2022-08-22 17:16:12 +00:00
David Harris
2e20b3ed72 Removed 2-cycle FPU-IEU latency stall 2022-08-22 16:14:15 +00:00
David Harris
bdfc49f847 moved CSA to generic 2022-08-22 08:41:23 +00:00
David Harris
f10793e85d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-22 08:28:31 +00:00
David Harris
f6f09db4fb Commented out unused comparators 2022-08-22 08:28:28 +00:00
Ross Thompson
dbbb3ff1d1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-21 16:03:11 -05:00
Ross Thompson
ebe4339953 Updated fpga test bench. 
Solved read delay cache bug.  Introduced during cache optimizations.
 2022-08-21 15:59:54 -05:00
Ross Thompson
85dbec5969 Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation. 2022-08-21 15:28:29 -05:00
Ross Thompson
f3f0f12904 Removed logic from Verilog wrapper. 2022-08-21 14:07:43 -05:00
Ross Thompson
82cce9a627 Updated fpga testbench. 2022-08-21 14:07:26 -05:00
Katherine Parry
a191603a1a fixed -1 issue in division 2022-08-20 00:53:45 +00:00
Ross Thompson
2ba390adf4 Possible reduction of ignorerequest. 2022-08-19 18:07:44 -05:00
Ross Thompson
517c0f6c35 Changed signal names. 2022-08-17 16:12:04 -05:00
Ross Thompson
f6e5746e59 Better name for LSUBusWriteCrit. Changed to SelLSUBusWord. 2022-08-17 16:09:20 -05:00
Ross Thompson
299aefb76a Removed old code from interlockfsm. 2022-08-17 12:52:56 -05:00
Katherine Parry
9549c23f45 sqrt tests in regression uncommented and pass 2022-08-07 23:38:10 +00:00
Katherine Parry
cb0c1b7488 radix-2 1 copy passes testfloat 2022-08-06 22:54:05 +00:00
Katherine Parry
de6ae471bc fixed fsw problem and removed 2 bit shift from shift correction 2022-08-03 22:16:51 +00:00
David Harris
898dbc8e74 Completed PLIC-S tests. Regression working. This completes peripheral tests. 2022-08-03 09:33:56 -07:00
David Harris
7e5b78f240 plic-s debug 2022-08-03 12:33:09 +00:00
David Harris
e70b28f7f6 FMA cleanup 2022-08-02 07:42:32 -07:00
David Harris
2b932c4b80 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-02 07:34:12 -07:00
David Harris
887e4c73fb Moved InvA to sign block; simplified fmaexpadd coding 2022-08-02 07:34:09 -07:00
Ross Thompson
413a9bf58b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 22:09:11 -05:00
Ross Thompson
57fcf0ef79 Fixed fstore2 in cache? 2022-08-01 22:04:44 -05:00
David Harris
06c4f18cd1 merged lza back into main 2022-08-01 19:45:21 -07:00
David Harris
8147f75399 Fixed fmaadd to work with new LZA 2022-08-01 19:40:55 -07:00
Ross Thompson
797d9e3610 Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris. 2022-08-01 21:12:25 -05:00
Ross Thompson
3cd8404917 Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask. 2022-08-01 21:08:14 -05:00
Ross Thompson
3612db2d70 pulled swbbytemask out of subword write. 2022-08-01 20:48:45 -05:00
David Harris
7e4b04ff64 Parameterized fmalza 2022-08-01 16:18:02 -07:00
David Harris
94fa7a00e7 Completed LZA simplificaiton 2022-08-01 16:13:16 -07:00
David Harris
3b937b73fd lza cleanup 2022-08-01 16:01:02 -07:00
David Harris
b614f165fb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 15:47:58 -07:00
David Harris
91597bba87 lza cleanup 2022-08-01 15:47:03 -07:00
David Harris
f56b26ec40 lza cleanup 2022-08-01 15:43:48 -07:00
David Harris
c3e9719c99 lza cleanup 2022-08-01 15:40:12 -07:00
David Harris
d6b5e7a6ef lza cleanup 2022-08-01 15:37:09 -07:00
Katherine Parry
8ff3a693af regression passes fpu tests 2022-08-01 19:56:25 +00:00
Katherine Parry
9c68f85822 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-01 19:55:50 +00:00
David Harris
2869d67e50 more lza cleanup 2022-08-01 12:34:00 -07:00
David Harris
b34d2065c3 LZA cleanup 2022-08-01 12:30:42 -07:00
David Harris
99462049e7 LZA refactoring switched to Pp1, Gm1, Km1 2022-08-01 12:20:23 -07:00
David Harris
3c08aabcd3 LZA refactoring 2022-08-01 11:36:21 -07:00
Katherine Parry
eddf6e9ee1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-01 18:35:07 +00:00
David Harris
7f9b601467 fmalza edits to match textbook 2022-08-01 18:23:39 +00:00
David Harris
257107f908 Partitioned fma into separate files 2022-08-01 18:07:38 +00:00
Ross Thompson
1ee613ae6c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-31 12:48:51 -05:00
Katherine Parry
1bd6351e1f re-added FStore2 in Cache 2022-07-29 22:54:49 +00:00
David Harris
93d7d7179e Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
David Harris
75a265159b Increased timeout threshold to avoid timeout building riscof tests on slow machine 2022-07-27 04:05:21 +00:00
David Harris
9ecef0c4cd fixed testbench merge comflict 2022-07-26 06:21:46 -07:00
David Harris
2d7f4b133c More work toward riscof tests 2022-07-26 06:19:13 -07:00
David Harris
766252db1b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-25 23:29:08 +00:00
David Harris
5c54c5b521 Added rv32f tests to RV64gc 2022-07-25 23:29:05 +00:00
David Harris
c6a58eb5b6 Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd 2022-07-25 16:23:10 -07:00
David Harris
416f5edfe0 More riscof makefile tuning 2022-07-25 21:15:56 +00:00
David Harris
7f7b3359b0 Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings 2022-07-25 20:50:38 +00:00
Ross Thompson
40e7cda84a Don't use this commit yet. Untested. 2022-07-24 15:40:52 -05:00
Ross Thompson
719b00e338 Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested. 2022-07-24 01:20:29 -05:00
Ross Thompson
69d520a7eb Removed replay from the config files. 2022-07-24 00:34:11 -05:00
Ross Thompson
f3cf46d633 Added more i-cache signals to wave file. 2022-07-24 00:24:13 -05:00
Ross Thompson
cd68896637 Merged evict dirty clear with flush write back. 2022-07-24 00:22:43 -05:00
Ross Thompson
8193946996 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-23 08:41:59 -05:00
Ross Thompson
05484c4c05 signal name cleanup. 2022-07-22 23:36:27 -05:00
Ross Thompson
27e32980ad cache cleanup after removing replay on cpubusy. 2022-07-22 23:30:25 -05:00
Ross Thompson
17ae1a1b1b cache fsm cleanup after removal of replay. 2022-07-22 23:25:09 -05:00
Ross Thompson
abc79c6c8e Possible improvement to cache which removes the cpu_busy states. 2022-07-22 23:20:37 -05:00
Katherine Parry
655e2d3810 merged radix-2 sqrt into divider - doesnt work yet 2022-07-23 00:41:18 +00:00
slmnemo
bfced6bfe8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
ca4511b6dc Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Daniel Torres
d0aaae26fe fixed wally rv32e tests, updated regression makefile to new testflow 2022-07-22 17:09:46 -07:00
Katherine Parry
b3d932cd61 divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
Daniel Torres
24828db612 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
Daniel Torres
4198145ce2 added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail 2022-07-22 14:58:55 -07:00