Daniel Torres
|
1fab7605f5
|
fixed issue where the unused spike elf files were being used to find objdump files that didn't exist causing makefile-memfile to fail prematurely
|
2022-06-21 15:39:04 -07:00 |
|
Madeleine Masser-Frye
|
6229779b97
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-21 20:31:06 +00:00 |
|
Madeleine Masser-Frye
|
3c08861479
|
switched comparator to dc flip version
|
2022-06-21 20:30:33 +00:00 |
|
James Stine
|
b1f12f3345
|
Add hex output in bad but okay way
|
2022-06-21 15:07:24 -05:00 |
|
James Stine
|
ca0815ce0d
|
Add MATLAB scripts for PD plot
|
2022-06-21 10:14:53 -05:00 |
|
slmnemo
|
80a57d0469
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-21 02:16:26 -07:00 |
|
slmnemo
|
b2cea45de0
|
Added rudimentary GPIO test according to testplans in chapter 15
|
2022-06-21 02:16:21 -07:00 |
|
Katherine Parry
|
0c6d36bbb2
|
made fixes to radix-2 divider testbench - divider doesn't pass
|
2022-06-20 23:01:53 +00:00 |
|
Katherine Parry
|
a0abfdefe6
|
radix-4 divider passing tests
|
2022-06-20 22:56:08 +00:00 |
|
Katherine Parry
|
03d823f5d7
|
added fld in rv32 - needs testing
|
2022-06-20 22:53:13 +00:00 |
|
James Stine
|
46bf9c351c
|
Update C program for r=4 division by recurrence to match Table in EL
|
2022-06-20 11:32:40 -05:00 |
|
Daniel Torres
|
397783812d
|
embench and testbench now support running both O2 and Os build variations without overwriting one another
|
2022-06-17 21:15:42 -07:00 |
|
Daniel Torres
|
1d4c543f71
|
arch tests now run on spike and sail and compare signatures during build
|
2022-06-17 20:53:15 -07:00 |
|
Daniel Torres
|
0ede7c412e
|
removed old code from makefile, simplified code in testbench
|
2022-06-17 15:13:38 -07:00 |
|
Daniel Torres
|
475220a5ff
|
arch bug fixes and testbench changes
|
2022-06-17 15:07:16 -07:00 |
|
Katherine Parry
|
2a8c17170c
|
hopefully fixed lint error
|
2022-06-17 00:14:39 +00:00 |
|
Katherine Parry
|
c9cbf6082d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-15 22:58:42 +00:00 |
|
Katherine Parry
|
0ffaec850b
|
postprocess out of fpu critical path
|
2022-06-15 22:58:33 +00:00 |
|
Madeleine Masser-Frye
|
154a1c80c1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-15 18:30:27 +00:00 |
|
Madeleine Masser-Frye
|
84256924e7
|
cleanup, plots for paper
|
2022-06-15 18:28:36 +00:00 |
|
James Stine
|
c660403ff2
|
Add back SV for integer division to use 8-bit CPA in qslc
|
2022-06-15 11:46:39 -05:00 |
|
James Stine
|
a078015271
|
Add r=4 C code
|
2022-06-15 11:44:09 -05:00 |
|
Katherine Parry
|
08b2481917
|
some synth fpu optimizations
|
2022-06-14 23:58:39 +00:00 |
|
Katherine Parry
|
8e19331ad5
|
removed false critical path from fpu
|
2022-06-14 16:50:46 +00:00 |
|
Katherine Parry
|
674c31ce59
|
fixed acciedental critical path in FPU
|
2022-06-14 00:02:38 +00:00 |
|
DTowersM
|
7c0f4dd954
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-13 23:34:35 +00:00 |
|
DTowersM
|
39ed36d0ba
|
added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
|
2022-06-13 23:23:57 +00:00 |
|
Katherine Parry
|
5f7072bd96
|
postprocessing unit created and passing all tests
|
2022-06-13 22:47:51 +00:00 |
|
David Harris
|
802bfd74fb
|
Cleanup on RAM module
|
2022-06-13 19:37:43 +00:00 |
|
David Harris
|
3c44b5842b
|
Typo in gpio reset
|
2022-06-13 19:37:05 +00:00 |
|
slmnemo
|
3626d5880e
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-13 12:30:33 -07:00 |
|
David Harris
|
9e1ec0255f
|
Removed SRT testvectors from repo
|
2022-06-13 19:27:33 +00:00 |
|
slmnemo
|
05a217c7e7
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-13 12:27:23 -07:00 |
|
slmnemo
|
c5d2037a7f
|
Merge branch 'cacheburstmode' into main.
Cache burst mode is now working! It also uses the new RAM.
|
2022-06-13 12:26:18 -07:00 |
|
slmnemo
|
a21d731834
|
Added more comments
|
2022-06-13 12:26:08 -07:00 |
|
David Harris
|
9080e35e54
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-13 19:26:07 +00:00 |
|
David Harris
|
09d72a33c5
|
Fixed XOR logic in GPIO
|
2022-06-13 19:26:03 +00:00 |
|
slmnemo
|
9f4ca06f7f
|
Added comment about name of LSUBusInit/Lock signal
|
2022-06-13 10:56:02 -07:00 |
|
slmnemo
|
a79737e95b
|
Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
|
2022-06-10 20:43:56 -07:00 |
|
slmnemo
|
d6a1ee1141
|
Added comments to signals added so the bus is easier to analyze
|
2022-06-10 20:30:04 -07:00 |
|
slmnemo
|
31852fdb19
|
Fixed failed regression state by only enabling counting when doing cached operations
|
2022-06-10 20:00:09 -07:00 |
|
slmnemo
|
0e10435fb6
|
Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01.
|
2022-06-10 19:10:01 -07:00 |
|
Madeleine Masser-Frye
|
032385aee3
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-10 21:11:47 +00:00 |
|
Madeleine Masser-Frye
|
374dfd1fc2
|
added 'd' suffix to muxes for data-critical synths
|
2022-06-10 21:11:05 +00:00 |
|
DTowersM
|
a61d1ab087
|
simplified coremark
|
2022-06-10 19:15:17 +00:00 |
|
slmnemo
|
5ac17eca1d
|
Passed Regression: Seems to work perfectly fine
|
2022-06-09 18:21:13 -07:00 |
|
slmnemo
|
75dffe4dcc
|
Merge branch 'main' into cacheburstmode
|
2022-06-09 17:51:03 -07:00 |
|
slmnemo
|
a4c7d1d936
|
?
|
2022-06-09 17:50:47 -07:00 |
|
DTowersM
|
d280f10a8d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-10 00:38:07 +00:00 |
|
DTowersM
|
4e5d7ec3d6
|
changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
|
2022-06-10 00:37:53 +00:00 |
|