Jordan Carlin
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6d77b22281
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Automatically determine number of threads to use in wally-tool-chain-install
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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602d126776
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Build nproc linux
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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c8519ce54f
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Build testvectors with buildroot
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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04b8739756
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Add cpio to installation for buildroot
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2024-07-24 19:55:18 -07:00 |
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David Harris
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5ac02c79c6
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Merge pull request #892 from ross144/main
Adds synthesizable RVVI FPGA hardware
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2024-07-24 12:21:36 -07:00 |
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Rose Thompson
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5a6e32576d
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Fixed the reset bug in wallyTracer.
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2024-07-24 13:32:46 -05:00 |
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Rose Thompson
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994386f12c
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Removed unused file.
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2024-07-24 13:30:25 -05:00 |
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Rose Thompson
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9053923d92
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-07-24 13:14:25 -05:00 |
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Rose Thompson
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13db14db6b
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Factored out the rvvi testbench code into rvvitbwrapper.
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2024-07-24 13:10:57 -05:00 |
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Rose Thompson
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c11036358a
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Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
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2024-07-24 12:47:50 -05:00 |
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Rose Thompson
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fb1869fcb9
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Updated verilog-ethernet to remove all verilator warnings or at least suppress them.
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2024-07-24 10:13:03 -05:00 |
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Jordan Carlin
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07ac498623
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Switch to logger function and fix exit codes
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2024-07-23 23:42:03 -07:00 |
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Jordan Carlin
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4c0265f67d
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Update logging grep
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2024-07-23 23:40:42 -07:00 |
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Jordan Carlin
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76277d1e7d
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Fix logging
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2024-07-23 23:40:03 -07:00 |
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Jordan Carlin
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790f566eaa
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Remove hardcoded /opt/riscv
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2024-07-23 23:29:45 -07:00 |
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Rose Thompson
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7960f26e84
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Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.
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2024-07-23 17:44:37 -05:00 |
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Rose Thompson
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35efbd6a54
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Changes are confirmed to work on the FPGA.
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2024-07-23 17:39:38 -05:00 |
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Jacob Pease
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c18b3d814d
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Fixed verilog bugs.
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2024-07-23 17:26:39 -05:00 |
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Jacob Pease
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23d9c7a486
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Fixed syntax bugs. inline functions are now static and in the spi.h header.
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2024-07-23 17:00:32 -05:00 |
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Rose Thompson
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bfb3b63a24
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Code cleanup.
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2024-07-23 16:35:05 -05:00 |
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Jacob Pease
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692bbc35fd
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Initial pass on SPI based bootloader code finished.
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2024-07-23 16:33:49 -05:00 |
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Jacob Pease
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659f0d3646
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Added some minor error checking to gpt.c.
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2024-07-23 16:32:52 -05:00 |
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Jacob Pease
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fe0f6de2ab
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Added sd_read64 to help with block reads and crc checking.
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2024-07-23 16:32:29 -05:00 |
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Rose Thompson
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fe9ac36928
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Fixed rvvi csr counting.
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2024-07-23 16:22:23 -05:00 |
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Rose Thompson
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da2511c63c
|
Fixed bugs in the rvvi synth logic which encoded csr instructions.
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2024-07-23 16:16:11 -05:00 |
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Jacob Pease
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a95106b516
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Progress made on implementing new disk read function.
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2024-07-23 15:47:23 -05:00 |
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Jacob Pease
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db13ed63b9
|
Removed references to card_type.
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2024-07-23 15:46:18 -05:00 |
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Jacob Pease
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2c35790359
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Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
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2024-07-23 14:18:50 -05:00 |
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Jacob Pease
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188df61037
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Added uart print functions and the Wally banner. SD card can now be initialized. Removed old code from boot.c
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2024-07-23 14:18:42 -05:00 |
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Rose Thompson
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7bc04702a7
|
Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.
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2024-07-23 13:18:03 -05:00 |
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Rose Thompson
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f20b82b14e
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Moved all rvvi files to rvvi directory.
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2024-07-23 13:03:21 -05:00 |
|
Rose Thompson
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d706b5b898
|
Fixed bus width error. Have to check this FPGA to make sure this didn't break anything.
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2024-07-23 12:26:03 -05:00 |
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Rose Thompson
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b30656447f
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Resolved more lint errors in the rvvi synthesized hardware.
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2024-07-23 12:23:04 -05:00 |
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Rose Thompson
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ebd8082508
|
Merge pull request #891 from davidharrishmc/dev
Increased covergen.py functional coverage to 87.6%
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2024-07-23 09:34:13 -05:00 |
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David Harris
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b7fb786749
|
Increased covergen.py functional coverage to 87.6%
|
2024-07-23 04:38:13 -07:00 |
|
Jordan Carlin
|
37046f4ff3
|
Fix minimum scipy version for Ubuntu20.04
|
2024-07-23 01:03:10 -07:00 |
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Jordan Carlin
|
23ceb2532e
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Fix python version for Ubuntu 20.04
|
2024-07-23 00:16:27 -07:00 |
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Jordan Carlin
|
9dad0aea1d
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Add logs and reduce console output
|
2024-07-22 23:13:38 -07:00 |
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Jordan Carlin
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2c08406b7f
|
Update python versions
|
2024-07-22 23:12:48 -07:00 |
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Jordan Carlin
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a2b9e34682
|
Use requirements file for pip packages
|
2024-07-22 23:12:27 -07:00 |
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Jordan Carlin
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f20edbf22e
|
Add DEBIAN_FRONTEND=noninteractive to apt
|
2024-07-22 23:11:33 -07:00 |
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Jordan Carlin
|
23b7d2059f
|
Update section header function usage
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2024-07-22 23:10:45 -07:00 |
|
Rose Thompson
|
c6c2240630
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-07-22 17:48:34 -05:00 |
|
Rose Thompson
|
5381e1f395
|
Updated for a better ILA rvvi debugger.
|
2024-07-22 17:44:04 -05:00 |
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Jacob Pease
|
ef1f55626c
|
Added sd_cmd and utility SPI functions.
|
2024-07-22 16:57:04 -05:00 |
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Rose Thompson
|
3c06556833
|
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
|
2024-07-22 16:12:06 -05:00 |
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Jacob Pease
|
c50df29e58
|
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
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2024-07-22 13:06:05 -05:00 |
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Jacob Pease
|
4585ad8891
|
Added new SDC clock constraint.
|
2024-07-22 13:05:16 -05:00 |
|
Jacob Pease
|
a722c3c0a1
|
Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.
|
2024-07-22 12:36:39 -05:00 |
|
Rose Thompson
|
35e69944fa
|
Cleaned up rvvisynth.sv
|
2024-07-22 12:22:41 -05:00 |
|