14 Commits

Author	SHA1	Message	Date
David Harris	d3ce683e06	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
David Harris	98176665de	Fixed messed-up hazard.sv	2023-11-15 08:05:41 -08:00
David Harris	8ba0336c6f	Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e	2023-11-14 11:01:58 -08:00
Rose Thompson	3322ff915e	Cleaned up the implementation changes for wfi.	2023-10-24 23:11:48 -05:00
Rose Thompson	c58f04c901	This version passes the regression test and solves issue #200. wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps.	2023-10-24 22:58:26 -05:00
Rose Thompson	c61526d034	Possible fix for wfi.	2023-10-24 18:08:33 -05:00
Ross Thompson	5f5f33787d	MDU and hazard unit now also parameterized. Based on Lim's work. Again I want to clarify this their work. Not mine. I'm just doing this because the merge had an issue.	2023-05-24 15:01:35 -05:00
Limnanthes Serafini	b3976daccd	More cleanup	2023-04-13 21:34:50 -07:00
David Harris	5cdd3d57c7	Commented WFI non-flush in writeback stage of hazard unit	2023-04-07 21:27:13 -07:00
David Harris	4552f9cf8c	Fixed WFI to commit when an interrupt occurs	2023-04-04 09:32:26 -07:00
David Harris	fd0c9e973d	Coverage improvements in ieu, hazard units	2023-03-31 08:33:46 -07:00
Ross Thompson	3d37d2769a	Book updates.	2023-03-14 13:09:50 -05:00
Ross Thompson	318189e5e6	Signal name changes.	2023-02-27 00:39:19 -06:00
David Harris	78eb90715c	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00