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Author SHA1 Message Date
Ross Thompson
eb5fb07f54 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-08-01 11:04:26 -05:00
Ross Thompson
6ca036fab3
Merge pull request #375 from JacobPease/main 
Updated Linux and Buildroot versions
 2023-08-01 11:57:55 -04:00
Jacob Pease
78ea821f2c Updated linux and buildroot configs initial commit. 2023-08-01 10:55:46 -05:00
Jacob Pease
923427490e Merge branch 'main' of github.com:openhwgroup/cvw 2023-08-01 10:47:59 -05:00
Ross Thompson
1b237a14a1 Pushed performance of arty a7 to 23Mhz. 2023-07-31 14:13:09 -05:00
Ross Thompson
3e66653f37 Cache cleanup. 2023-07-31 14:12:53 -05:00
Ross Thompson
141e90d425
Merge pull request #372 from davidharrishmc/dev 
PLIC part select warnings fixed
 2023-07-31 11:28:28 -04:00
David Harris
55d4f28efe
Merge pull request #373 from harshinisrinath1001/main 
Improved testing of pmd in priv, fixed bugs, and attempted to reset menvcfg and fixed spacing in fpu/fma and fpu/postprocessing
 2023-07-30 22:46:44 -07:00
Harshini Srinath
01fc7c5284
Fixed formatting 2023-07-30 18:36:25 -07:00
Harshini Srinath
811e2fd94c
Fixed formatting 2023-07-30 18:30:23 -07:00
Harshini Srinath
2194f7d604
Fixed formatting 2023-07-30 18:28:27 -07:00
Harshini Srinath
01bbddc5da
Fixed formatting 2023-07-30 18:27:22 -07:00
Harshini Srinath
ef39e7cb92
Fixed formatting 2023-07-30 18:20:38 -07:00
Harshini Srinath
a697c89a2a
Fixed formatting 2023-07-30 18:18:24 -07:00
Harshini Srinath
1bc1a68210
Fixed formatting 2023-07-30 18:06:25 -07:00
Harshini Srinath
86164acc84
Fixed formatting 2023-07-30 18:00:39 -07:00
Harshini Srinath
6b5aa47f23
Fixed formatting 2023-07-30 17:54:47 -07:00
Harshini Srinath
8c7ea5a47a
Fixed formatting 2023-07-30 17:46:23 -07:00
Harshini Srinath
69711503a8
Fixed formatting 2023-07-30 17:39:37 -07:00
Harshini Srinath
70599d3153
Fixed formatting 2023-07-30 17:38:22 -07:00
Harshini Srinath
2846a2f567
Fixed spacing 2023-07-30 17:32:46 -07:00
Harshini Srinath
fffde4ef7d
Fixed spacing 2023-07-30 17:22:40 -07:00
Harshini Srinath
31c09cf3cf
Fixed spacing 2023-07-30 17:21:52 -07:00
Harshini Srinath
c49944a495
Fixed spacing 2023-07-30 17:21:22 -07:00
Harshini Srinath
84d72bc203
Fixed spacing 2023-07-30 17:18:25 -07:00
Harshini Srinath
b8570c4bef
Fixed spacing 2023-07-30 16:59:27 -07:00
Harshini Srinath
872f9ed9cc
Fixed spacing 2023-07-30 16:57:57 -07:00
harshinisrinath
15dbbef9ad Fixed bug and tried to reset menvcfg to improve testing of csri in priv. 2023-07-30 16:40:06 -07:00
David Harris
f7f4c5fa7b renamed test-shared.vh to config-shared.vh 2023-07-30 05:22:39 -07:00
David Harris
388d699baa Cleaned up lint for plic_apb part select 2023-07-30 02:00:38 -07:00
David Harris
54d6a1afa2 Fixed Questa warnings in plic_apb about part select out of bounds 2023-07-30 01:54:41 -07:00
Jacob Pease
6c8bbf7f13 Merge branch 'main' of github.com:openhwgroup/cvw 2023-07-28 12:49:19 -05:00
David Harris
5fa84ddac4
Merge pull request #371 from ross144/main 
Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv.  STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop.
 2023-07-28 09:51:58 -07:00
Ross Thompson
84600937c8 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-28 11:23:17 -05:00
Ross Thompson
8d88ef93bc Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop. 2023-07-28 11:20:29 -05:00
Jacob Pease
d3476b64cd Updated VCU108 device tree for 256MB memory. 2023-07-27 17:44:31 -05:00
Ross Thompson
e4327d3489
Merge pull request #370 from JacobPease/main 
Fixed GPIO pin names in fpgaTop.v
 2023-07-27 16:10:44 -04:00
Jacob Pease
87a6ad5a87 Removed non-existent SDC dependency from VCU targets in FPGA Makefile. 2023-07-27 15:01:20 -05:00
Jacob Pease
f696cf9955 Merge branch 'main' of github.com:openhwgroup/cvw 2023-07-27 14:46:01 -05:00
David Harris
746891eac5
Merge pull request #369 from ross144/main 
Fixed issue #368 lint, but not simulation
 2023-07-26 13:32:02 -07:00
Ross Thompson
52dc71507f Fixed lint errors for issue #368. Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN. 2023-07-26 15:08:01 -05:00
Jacob Pease
8b97d323e0 Fixed GPIO pin names in fpgaTop.v 2023-07-25 20:57:04 -05:00
David Harris
6e0d5d9962
Merge pull request #367 from ross144/main 
Complete removal of old flash card hardware and updates to Arty A7 to push clock speed to 20Mhz and increase memory to 256 MiB
 2023-07-25 15:26:08 -07:00
Ross Thompson
1b8edacd8d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-25 15:13:07 -05:00
Ross Thompson
8dc7870e62 Updated Arty A7 fpga config and device tree to 256MiB main memory. 2023-07-25 15:11:47 -05:00
Ross Thompson
97540791de
Merge pull request #366 from davidharrishmc/dev 
Progress toward DC synthesis
 2023-07-25 11:39:49 -04:00
David Harris
0cfb5c7b3a Formatting cleanup 2023-07-25 05:11:38 -07:00
David Harris
f2623a7229 Progress toward synthesis with parameterized design 2023-07-25 05:10:53 -07:00
Ross Thompson
a543aa2b71 Removed old sdc from all configs. 2023-07-24 15:55:22 -05:00
Ross Thompson
717833b11a Removed all old references to the old flash card controller. 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
 2023-07-24 15:45:57 -05:00