Domenico Ottolia
280cd94280
Make privileged makefiles actually execute tests when you say they should (compile-only is still default)
2021-04-27 23:09:01 -04:00
Domenico Ottolia
1c30625382
Modify make file to make privileged tests always pass Imperas (for testing interrupts) & Add mtvec/stvec tests
2021-04-27 21:47:38 -04:00
Noah Boorstin
fce3d6a8b1
busybear: respect branch predictor disable config
2021-04-27 15:52:18 -04:00
Ross Thompson
d191bc6cc1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-26 14:28:09 -05:00
Ross Thompson
14a69c1d06
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Noah Boorstin
922c8e450f
ok but do that better
2021-04-26 14:38:05 -04:00
Noah Boorstin
24bbb674d3
linux: start using internal branch predictor signal
2021-04-26 14:34:38 -04:00
Ross Thompson
a7e4d39ea1
Fixed issue with not saving the first cache block read on a miss spill.
2021-04-26 12:57:34 -05:00
Noah Boorstin
9cbc769083
minor busybear fixes
2021-04-26 13:24:39 -04:00
Noah Boorstin
2e9bef1d75
minor parsing updates
2021-04-26 13:11:01 -04:00
Ross Thompson
44d28dbd1c
Icache integrated!
...
Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
Ross Thompson
615831f588
Reverted back the exe2memfile.pl script changes. Something I changed broke the load tests.
2021-04-26 10:44:27 -05:00
bbracker
f921886451
merge cleanup; mem init is broken
2021-04-26 08:00:17 -04:00
bbracker
7947858481
it says I need to merge in order to pull
2021-04-26 07:46:24 -04:00
bbracker
8d77012995
progress on bus and lrsc
2021-04-26 07:43:16 -04:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Noah Boorstin
91df7b1f8b
buildroot: change to new image
2021-04-25 15:15:14 -04:00
Noah Boorstin
76810f8423
busybear: hopefully last parser changes of the semester
2021-04-25 14:08:18 -04:00
Noah Boorstin
0ecb114dd6
parsing scripts update
2021-04-24 21:56:16 -04:00
bbracker
46a1616079
thomas fixed it before I did
2021-04-24 09:38:52 -04:00
bbracker
5687ab1c96
do script refactor
2021-04-24 09:32:09 -04:00
Thomas Fleming
ff675a5647
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-23 20:12:27 -04:00
Thomas Fleming
dc3ffc9244
Add address translation to busybear testbench
2021-04-23 20:12:20 -04:00
Thomas Fleming
6f23858609
Fix HSIZE and HBURST signal widths in PMA checker
2021-04-23 20:11:43 -04:00
David Harris
9c9fe56292
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-23 19:04:29 -04:00
David Harris
e3b28db969
Fixed exe2memfile.pl to handle large files
2021-04-23 19:04:16 -04:00
Ross Thompson
d7fea1ba3c
almost working icache.
2021-04-23 16:47:23 -05:00
Noah Boorstin
50df9d11e1
busybear
2021-04-23 17:32:37 -04:00
Shriya Nadgauda
26b8d69001
pipeline testing additonal files
2021-04-23 15:46:02 -04:00
Shriya Nadgauda
2a5c243b0b
adding pipeline testing
2021-04-23 14:19:17 -04:00
Jarred Allen
9a88d83851
Remind people to run make allclean when a regression fails
2021-04-22 19:21:00 -04:00
Ross Thompson
c9bdaceddb
Fixed icache for 32 bit.
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Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Ross Thompson
04eb302925
Yes. The hack to not repeat the d memory operation fixed this issue.
2021-04-22 15:22:56 -05:00
Thomas Fleming
5bff582608
Write PCM to TVAL registers
2021-04-22 16:17:57 -04:00
Thomas Fleming
07770a46d8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-22 15:37:19 -04:00
Thomas Fleming
74fb1dccad
Prepare to squash bad ahb accesses
2021-04-22 15:36:45 -04:00
Thomas Fleming
c055ab272d
Clean up lint errors in fpu and muldiv
...
booth.sv had an actual error where a signal was being assigned to too
many bits. muldiv has a lot of non blocking assignments, so I suppressed
those warnings so the linter output was readable.
2021-04-22 15:36:03 -04:00
Domenico Ottolia
787ae978d7
Fix misa synthesis bug (for real now)
2021-04-22 15:35:20 -04:00
Thomas Fleming
e7822ce20c
Implement first pass at the PMA checker
2021-04-22 15:34:02 -04:00
Thomas Fleming
848508530c
Pass lint-wally arguments to verilator
2021-04-22 13:39:20 -04:00
Jarred Allen
8baa2a350d
Add buildroot to regression test
2021-04-22 13:34:56 -04:00
Thomas Fleming
805ac5dbd7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-22 13:20:12 -04:00
Thomas Fleming
f9e071baf8
Temporarily disable rv64 mmu test
...
Will restore once cache revamp is pushed
2021-04-22 13:19:18 -04:00
Noah Boorstin
3bf79923d4
small parser fix
2021-04-22 12:06:54 -04:00
bbracker
c796547156
greatly improved PLIC register interface
2021-04-22 11:22:01 -04:00
Ross Thompson
7c8d2e9b78
Partially working icache.
...
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory. This keeps StallF high and
the icache FSM is never allowed to complete.
2021-04-22 10:20:36 -05:00
Thomas Fleming
d22f0f9d63
Refactor tlb_ram to use flop primitives
2021-04-22 01:52:43 -04:00
Thomas Fleming
4d4ca24640
Extend stall on leaf page lookups
2021-04-22 01:51:38 -04:00
Domenico Ottolia
939e36a151
Fix misa bug
2021-04-22 00:59:07 -04:00
Thomas Fleming
88bd151d55
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ifu/ifu.sv
2021-04-21 20:01:08 -04:00
