Ross Thompson
755c3e6a4c
Fixed buildroot to work with the fpga's merge.
2021-12-02 18:09:43 -06:00
Ross Thompson
74ffb48c0a
Mostly integrated FPGA flow into main branch. Not all tests passing yet.
2021-12-02 18:00:32 -06:00
Ross Thompson
b7e8c74e61
Merge branch 'fpga' into main
2021-12-02 14:28:10 -06:00
David Harris
e4861e11d1
Added coremark scripts to regression directory
2021-12-01 09:08:06 -08:00
Ross Thompson
8e4eacc18e
Merge branch 'main' into fpga
2021-11-29 10:10:37 -06:00
Ross Thompson
e43aa6ead4
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
bbracker
de8e2008d2
fix parseState.py to correctly take in PMPCFG
2021-11-24 16:52:51 -08:00
bbracker
9e4033935f
add checkpoints to regression
2021-11-20 19:42:53 -08:00
bbracker
685534fc20
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-19 20:25:06 -08:00
bbracker
42ba205c4f
automatic bug finder script
2021-11-19 20:25:00 -08:00
bbracker
5a2a2ca4f5
increase buildroot progress expecttions; increase timeout to 20 hours
2021-11-19 12:52:11 -08:00
David Harris
b996598b37
CoreMark testing
2021-11-18 16:14:25 -08:00
David Harris
b49c419d0b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:28:33 -08:00
Kevin Kim
d4e9376854
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 12:18:25 -08:00
Kevin Kim
34b3cc1c8d
root level makefile added
2021-11-17 12:17:56 -08:00
Kip Macsai-Goren
3f76549a7d
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
2021-11-17 10:53:17 -08:00
Ross Thompson
3b8bdc7b2d
Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
2021-11-17 12:47:19 -06:00
David Harris
5a521e28ee
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-16 12:30:55 -08:00
Ross Thompson
b8572d6a2a
Changed several things.
...
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
David Harris
f96152fa31
bringing Coremark back to life
2021-11-10 12:43:31 -08:00
Kevin Kim
a7684f1b59
Makefile added in regression directory:
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-cd's into imperas then runs make commands, finally running the tvLinker script
2021-11-09 10:55:48 -08:00
bbracker
1597e0dac6
increase expectations for buildroot and timeout count
2021-11-06 14:57:29 -07:00
bbracker
e4cf044932
fix testbench interrupt timing
2021-11-02 21:19:12 -07:00
David Harris
910957704b
Add3d wally32i test
2021-11-01 13:17:49 -07:00
David Harris
c306884e2c
Adding custom Wally test infrastructure
2021-11-01 08:48:46 -07:00
bbracker
38d26e857b
fix buildroot graphical sim
2021-10-31 18:33:43 -07:00
David Harris
717f9d48e9
tesgen cleanup, added riscv-arch-test D tests
2021-10-29 22:31:48 -07:00
David Harris
0421b7af56
Changes for floating point sims
2021-10-27 10:37:35 -07:00
David Harris
f793dd7a5e
removed unused signal from wave.do
2021-10-26 09:02:22 -07:00
bbracker
f39a509b5b
adapt testbench linux to use reset_ext
2021-10-25 13:26:44 -07:00
Ross Thompson
2f4ee26b60
Fixed issue with dtim (fpga) external abhlite select not triggering.
...
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
2021-10-25 14:51:54 -05:00
bbracker
2c9c9328a9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-25 12:25:37 -07:00
bbracker
c61cbf9618
change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
2021-10-25 12:25:32 -07:00
Ross Thompson
f7583d0e0d
Updated uncore to use sdc.
...
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
2021-10-25 14:07:44 -05:00
David Harris
47124f36c8
Added synchronizer to reset
2021-10-25 10:05:41 -07:00
bbracker
9423b90780
switch linux graphical sim over to Ross's waves
2021-10-24 18:39:23 -07:00
bbracker
4544d28bc9
or actually needed to reduce expectations of buildroot
2021-10-24 06:59:34 -07:00
bbracker
23bff55c6e
increase regression's expectations of buildroot
2021-10-24 06:50:22 -07:00
bbracker
366cb12a13
buildroot do scripts now compile flops
2021-10-23 23:14:59 -07:00
bbracker
3b63dde570
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-23 13:17:37 -07:00
bbracker
d6fb441666
add option for regression to do a partial execution of buildroot
2021-10-23 13:17:30 -07:00
David Harris
67f3fc9962
wrapping up lint cleanup; many unused signals removed
2021-10-23 12:15:14 -07:00
David Harris
bf3eb7b814
update scripts for handling src/*/* subdirectories
2021-10-23 08:54:29 -07:00
David Harris
8b854bb1c2
Cleaned up LINT erors
2021-10-23 06:28:49 -07:00
David Harris
3407b63c8a
Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.
2021-10-23 06:15:26 -07:00
Ross Thompson
09dc3e1143
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
Ross Thompson
77a89c30de
Fixed bug with the external memory region selection.
...
Updated bios program to copy just 127MB to dram.
2021-10-19 11:23:23 -05:00
James E. Stine
eb64a7f0c9
Update to fpdivsqrt to go on posedge as it should. Also an update to
...
individual regression test for TestFloat (still needs some tweaking)
2021-10-13 17:14:42 -05:00
bbracker
886a650da4
change infrastructure to expect only 6.3 million from buildroot
2021-10-12 10:41:15 -07:00
Ross Thompson
5fdac9fa3b
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
