15 Commits

Author	SHA1	Message	Date
David Harris	e084c8868f	Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion	2021-12-30 17:22:18 +00:00
David Harris	75b8e1f68e	Fixed lint for RV32IC by handling PMP_ENTRIES = 0 in csrm, but may have broken buildroot.	2021-12-30 02:38:42 +00:00
David Harris	26d6f8d51a	RV32ic tests running for simple machine with no privileged unit	2021-12-30 02:25:46 +00:00
David Harris	866a5efc43	rv32i regression and linting	2021-12-30 00:53:39 +00:00
David Harris	d78b806332	Added performance counting to sumtest and added imperas32/64periph to testbench.	2021-12-29 00:28:51 +00:00
David Harris	a7cfda8e52	Incorporated new Imperas tests. f and d tests are failing and c tests are hanging.	2021-12-26 04:36:53 +00:00
David Harris	e97e512da9	Started FIR test code and started incorporating Imperas tests	2021-12-25 22:39:51 +00:00
David Harris	f4957fdac1	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
David Harris	1ca949c0bb	Simplified ALU and source multiplexers pass tests	2021-12-13 07:57:38 -08:00
David Harris	b996598b37	CoreMark testing	2021-11-18 16:14:25 -08:00
David Harris	717f9d48e9	tesgen cleanup, added riscv-arch-test D tests	2021-10-29 22:31:48 -07:00
David Harris	0421b7af56	Changes for floating point sims	2021-10-27 10:37:35 -07:00
David Harris	a077735ecc	Major reorganization of regression and simulation and testbenches	2021-10-10 15:07:51 -07:00
Ross Thompson	7bc95ba073	Fixed issue with sim-wally-batch. Are people still using this script?	2021-03-17 11:17:52 -05:00
David Harris	bf07ec92b5	Added test configurations	2021-01-25 11:28:43 -05:00