David Harris
31adea3db0
Modified rams to take USE_SRAM rather than P to facilitate synthesis
2023-11-03 05:44:13 -07:00
David Harris
aa3bc10259
Modified log2 coding to avoid synthesis warning
2023-10-19 11:16:02 -07:00
Ross Thompson
7c89154a7f
Slight modification to cachefsm.
2023-09-05 14:07:58 -05:00
Ross Thompson
e39fc44efd
Merge pull request #406 from magpyed/cachesim_fix
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Properly gate LRUWriteEn with ~FlushStage
2023-09-05 11:10:58 -05:00
Limnanthes Serafini
b334e4ff1f
Properly gate LRUWriteEn with ~FlushStage
2023-09-01 23:31:02 -07:00
David Harris
98fa3a78dd
Improved tlb and controller coverage; fixed exclusions on broken lines
2023-08-31 00:27:47 -07:00
Ross Thompson
284ff0ab0b
Fixed minor performance bug with CBOZ.
2023-08-24 17:08:20 -05:00
Ross Thompson
fbcf6be06d
Now have CBOZ instructions working!
2023-08-24 16:47:35 -05:00
Ross Thompson
a899be7deb
Fixed bug with the cbo.inval clearing already cleared lines.
2023-08-21 17:51:51 -05:00
Ross Thompson
6337aab757
Fixed issue when with flush miss.
2023-08-18 16:36:13 -05:00
Ross Thompson
e3bb0d2820
Now we have invalidate, clean, and flush working.
2023-08-18 16:32:22 -05:00
Ross Thompson
b842fdb863
Might have working cbo clean and flush instructions.
2023-08-18 14:48:21 -05:00
Ross Thompson
8c7eafffad
Fixed cbo instruction decode.
2023-08-18 11:32:30 -05:00
Ross Thompson
bfde4d2c78
Found first bug in CMO implementation.
2023-08-17 16:57:54 -05:00
Ross Thompson
6a8a82d9e8
CMOZ now implemented in the D cache.
2023-08-17 12:46:40 -05:00
Ross Thompson
e74e4f3a60
Added clean and flush to cache fsm.
2023-08-16 14:23:56 -05:00
Ross Thompson
b5ca41fd2a
More progress towards cmo.
2023-08-15 18:17:15 -05:00
Ross Thompson
6284773733
The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush.
2023-08-14 16:39:18 -05:00
Ross Thompson
f678133d19
Initial CMO implementation. Just adds control signals into the L1 caches.
2023-08-14 15:43:12 -05:00
Ross Thompson
3e66653f37
Cache cleanup.
2023-07-31 14:12:53 -05:00
Ross Thompson
37078f3d9b
Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
2023-07-21 13:06:27 -05:00
Ross Thompson
20751790f6
Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations.
2023-07-14 16:31:44 -05:00
Ross Thompson
c12bc4f435
Created separate temporary testbench for xcelium.
2023-07-11 15:07:33 -05:00
Ross Thompson
a011b7d591
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
44c72c20e2
Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.
2023-06-15 14:05:44 -05:00
Ross Thompson
2fc8080102
Got the srams parameterized correctly now.
2023-06-15 13:42:24 -05:00
Ross Thompson
e431f90cf3
Found a whole bunch of files still using the old `define configurations.
2023-06-15 13:09:07 -05:00
Harshini Srinath
b4e5f43acb
Update subcachelineread.sv
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Code clean up
2023-06-09 08:50:51 -07:00
Harshini Srinath
7475a0eeed
Update cacheway.sv
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Code clean up
2023-06-09 08:48:11 -07:00
Harshini Srinath
fcac659e34
Update cacheLRU.sv
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Code clean up
2023-06-09 08:43:38 -07:00
Harshini Srinath
1f1fcce062
Update cache.sv
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Formatting clean up
2023-06-09 08:39:57 -07:00
Ross Thompson
e33db7f9a7
More parameterization. Copied Lim. Still no slow down.
2023-05-24 14:49:22 -05:00
Ross Thompson
8eaa4bf075
Fixed bug in cacheLRU when NUMWAYS = 2.
2023-04-27 14:30:01 -05:00
Alec Vercruysse
6299c0ef0b
Cacheway Exclude FlushStage=1 when SetValidWay=1
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We determined that this case is not hit even for i$, so this
case is also excluded separately for i$. It could be a better
idea to remove the ~FlushStage check completely (if we're sure).
My reasoning for this one is written as a comment in the exclusion
script: since a pipeline stall is asserted by the cache in the fetch
stage (which happens before going into the WRITE_LINE state and
asserting SetValidWay), there seems to be no way to trigger
a FlushStage (FlushW for D$) while the stallM is active.
2023-04-25 20:30:46 -07:00
Alec Vercruysse
2f49ee18fe
Cacheway exclude SelFlush=0 while FlushWay=0 in FlushWayEn assign
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FlushWay is always 1 for one way, but by default it is only 1 for
way 0.
The logic that advances FlushWay to ways 1, 2, and 3 only does so
on a subset of conditions that SelFlush is high (in cachefsm), so
this is unreachable for cachways 1-3.
2023-04-25 17:02:53 -07:00
David Harris
0871bbe8f2
Fixted syntax error in exclusion. Arbitrarily picked -e 1; fix if this isn't right
2023-04-22 10:07:48 -07:00
Alec Vercruysse
7ba2bfd4b6
CacheFSM logic simplification for AMO operations
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Ran this by Ross.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
b52512b1ae
D$ scope-specific coverage exclusions (I$ logic that never fires)
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The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.
Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.
There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
2023-04-19 01:34:01 -07:00
Ross Thompson
a77d403e4c
Merge pull request #233 from AlecVercruysse/coverage3
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Full I$ coverage
2023-04-14 22:15:11 -05:00
Alec Vercruysse
862d1e0116
replace instances of code duplication for i$ exclusions w/commands
2023-04-14 17:10:39 -07:00
Limnanthes Serafini
5d12afa671
Some cleanup
2023-04-13 21:01:57 -07:00
Limnanthes Serafini
c427b4c896
Misc typo and indent fixing.
2023-04-13 16:54:15 -07:00
Alec Vercruysse
a3d9e11b0f
cachefsm exclude icache logic without code reuse
2023-04-12 15:57:45 -07:00
Alec Vercruysse
800f0245f3
Cachefsm gate LRUWriteEn with ~FlushStage
2023-04-12 13:32:36 -07:00
Alec Vercruysse
e303d99d5b
Merge branch 'main' into coverage3
2023-04-12 09:34:09 -07:00
Alec Vercruysse
d60e3aaf53
only assign ClearDirtyWay for read-write caches
2023-04-12 01:15:35 -07:00
Alec Vercruysse
729f81a0df
refactor cachefsm to get full coverage
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I had to exclude i$ states in coverage-exclusions-rv64gc.do,
but it's referred to by scope, which should be pretty robust
2023-04-12 01:15:35 -07:00
Alec Vercruysse
1ce2ab5daa
Coverage and readability improvements to LRUUpdate logic
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The genvar stuff was switched to readable names to make it easier
to understand for the first time. In the LRUUpdate logic for loop,
a special case was added for simpler logic in the case of the root
node, to hit coverage.
2023-04-12 01:15:35 -07:00
Alec Vercruysse
214abc7006
Make AdrSelMux and CacheBusAdrMux mux2 if READ_ONLY_CACHE
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Some address options are only used in the D$ case.
2023-04-12 01:15:35 -07:00
Alec Vercruysse
6dce58125b
Remove FlushStage Logic from CacheLRU
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For coverage.
LRUWriteEn is gated by FlushStage in cache.sv,
so removing the signal completely avoids future confusion.
Update cache.sv to reflect cacheLRU edit.
2023-04-12 01:15:35 -07:00
