Jacob Pease
142ec857ed
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
...
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
Jacob Pease
2ad9c72acc
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
Jacob Pease
53de2bf782
AHB triggers write, but AXI side doesn't update.
2023-04-18 15:23:22 -05:00
Jacob Pease
2b9e5608a4
Build doesn't work. AXI Crossbar has problems.
2023-04-06 16:01:58 -05:00
Jacob Pease
303c997a69
Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore
2023-03-24 17:01:27 -05:00
Jacob Pease
b2a5786cda
Disabled old SD card and attached IOBUF's to new SD peripheral.
2023-02-28 12:20:46 -06:00
Jacob Pease
2822cb273c
AXI Crossbar is working. Fixed address width in generator script.
2023-02-22 15:13:16 -06:00
Jacob Pease
5161fd25cc
Merge branch 'main' of github.com:openhwgroup/cvw into boot
2023-02-16 17:36:26 -06:00
Jacob Pease
c1e7526570
Fixed debug signal names. Builds on the fpga. Bug in the crossbar.
2023-02-16 17:33:21 -06:00
Ross Thompson
920bd40822
fpga constraints updates
2023-02-07 15:22:14 -06:00
David Harris
99d179dd3e
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
Jacob Pease
cfe792a814
Flipped crossbar inputs and outputs to correctly place masters.
2023-01-27 14:57:36 -06:00
Jacob Pease
eb3c6754f8
Removed IOBUF's from sdc_controller.
2023-01-27 14:35:34 -06:00
Jacob Pease
536039ad86
Modified makefile. Added axi protocol converter IP.
2023-01-23 19:30:29 -06:00
Jacob Pease
185e58ddcb
Created missing wires for axi interfaces in fpgaTop.v.
2023-01-23 19:02:01 -06:00
Jacob Pease
24d0b1c860
Added extra core signal to mark_debug.txt. Modified wally.tcl
2023-01-23 17:00:24 -06:00
Jacob Pease
204fb84708
Merge branch 'main' of github.com:openhwgroup/cvw into boot
2023-01-23 12:41:02 -06:00
Ross Thompson
64eaaa670c
More fixes for the debug2.xdc constraints.
2023-01-20 20:48:19 -06:00
Ross Thompson
ee4c78c7fa
More fixes to fpga ila debugger.
2023-01-20 20:28:21 -06:00
Ross Thompson
3effeb42c3
Fixed fpga constraints.
2023-01-20 20:18:04 -06:00
Ross Thompson
442de3f5b7
Updated fpga constraints.
2023-01-20 20:16:33 -06:00
Ross Thompson
a4822c9f54
Added license and comments to new script.
2023-01-20 19:50:33 -06:00
Ross Thompson
b709c224ab
Updated ignore to exclude copied files.
2023-01-20 19:47:33 -06:00
Ross Thompson
e06237ad92
Removed mark_debug vivado directive from source code.
...
Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger.
Files output to temporary directory.
2023-01-20 19:43:18 -06:00
Ross Thompson
9d8fed1d35
Test commit.
2023-01-20 17:27:09 -06:00
Ross Thompson
b25b93df11
Repaired fpga debugger.
2023-01-20 15:26:52 -06:00
Ross Thompson
3e1a54e80a
Removed SDC from repo due to copy right issue.
...
Modified fpga build flow to reference it outside the repo.
2023-01-20 14:57:06 -06:00
Jacob Pease
4af0633cee
Added IOBUFs to SDCDat. Edited debug2.xdc. Dwidth converter error.
2023-01-19 16:57:43 -06:00
Jacob Pease
dcb30dcfb2
Fixed errors in uncore and included newsdc stuff in wally.tcl
2023-01-17 16:46:00 -06:00
Jacob Pease
3b7e721823
Fixed typos. Apparently `defube causes a weird vivado error.
2023-01-13 16:59:18 -06:00
Jacob Pease
47c46bc9b5
Added IPs to wally.tcl.
2023-01-13 14:36:23 -06:00
Jacob Pease
b63927b474
Connected the axi_sdc_controller with an axi crossbar.
...
Added an adrdec.sv to the adrdecs.sv file for the sake of the
cache. Modified Uncore accordingly.
2023-01-13 13:56:01 -06:00
Ross Thompson
6cf5a99b5d
Updated constraints to remove DivBusyE.
2022-12-30 10:51:35 -06:00
Ross Thompson
967d892088
Updated fpga constraints.
2022-12-24 10:21:16 -06:00
Ross Thompson
a2de53aeeb
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
...
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
2cc4d66ded
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
Ross Thompson
b7224cc5ba
Updated fpga constraints.
2022-12-21 14:50:01 -06:00
Ross Thompson
e326c9972c
Updated vcu118 piniout.
2022-12-18 14:00:10 -06:00
Ross Thompson
9eac190468
Updated fpga constraints
2022-12-15 16:45:55 -06:00
rachanaerra
4f042b0adb
updated constraints file
2022-12-05 15:05:21 -06:00
Ross Thompson
55335d1db6
Updated top level fpga file.
2022-11-18 11:10:45 -06:00
Ross Thompson
8692bafd04
Updated fpga wave configuration.
2022-11-16 15:57:19 -06:00
Ross Thompson
3de5144ae4
Updated vcu118 constraints to run cpu at 38.43Mhz.
2022-11-15 10:19:38 -06:00
Ross Thompson
b812549f38
Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s).
...
Increased CPU clock speed from 30 Mhz to 35 Mhz.
2022-11-11 15:33:03 -06:00
Ross Thompson
ebfee753ca
Updates to fpga constraints.
2022-11-09 13:52:36 -06:00
Ross Thompson
fd1ef82310
Fixed bug with fpga makefile.
2022-11-07 09:20:05 -06:00
Jacob Pease
ec0cede2f2
Added PLIC signals for debugging on FPGA.
2022-10-25 13:57:09 -05:00
Ross Thompson
1510c2d92f
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 15:38:39 -05:00
Ross Thompson
ae01c8e824
Forget to include updated xdc file.
2022-10-24 13:51:21 -05:00
Ross Thompson
a45e612008
Updated debug2.xdc for interlock fsm changes.
2022-10-19 17:34:47 -05:00
