David Harris
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122ba0bf58
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Reset STIMECMP to 0 to agree with ImperasDV
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2023-11-21 13:43:51 -08:00 |
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David Harris
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d26c505a4d
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repo cleanup and start to add CMO tests
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2023-11-20 23:41:36 -08:00 |
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David Harris
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b9023af535
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Removed other unused signals from Verilog
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2023-11-20 23:37:56 -08:00 |
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David Harris
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b0f118a93a
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removed unused cache signals
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2023-11-20 23:16:35 -08:00 |
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David Harris
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f7fb30573f
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Merge pull request #491 from ross144/main
Running ImperasDV Linux is upto date
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2023-11-20 10:28:05 -08:00 |
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Rose Thompson
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7d467462d4
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-20 11:29:45 -06:00 |
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Rose Thompson
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d4865505b4
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Finally have the cbo way muxing controls reduced to something sane.
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2023-11-20 11:28:03 -06:00 |
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Rose Thompson
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199a84eee0
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-11-20 10:34:36 -06:00 |
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Rose Thompson
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aa6ee8ecdc
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-20 10:30:42 -06:00 |
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Rose Thompson
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bc41f12195
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Modified linux imperas tests to
1. enable zicclsm
2. enable logging at 7000 ms
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2023-11-20 10:30:35 -06:00 |
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Rose Thompson
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baf9546a73
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Merge pull request #490 from davidharrishmc/dev
Synthesis running for textbook, preload IROM to avoid it being optimized out, updated M tests in risk-arch-test
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2023-11-19 20:42:29 -08:00 |
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David Harris
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65a09a81e9
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Commented IROM preloading
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2023-11-19 19:33:57 -08:00 |
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Rose Thompson
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be672a0770
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Added menvcfg to debugger for checking what linux has configured.
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2023-11-19 13:44:22 -06:00 |
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David Harris
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b549c95bfd
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-19 06:49:25 -08:00 |
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David Harris
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9d3da4d1da
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wallySynthAll.sh automates running all synthesis experiments without maxopt
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2023-11-19 06:49:07 -08:00 |
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David Harris
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1b9c93e07a
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Changed rv32gc to do IDIV in MDU and have k=2 copies of FDIV stages; added correct sky130 adder data; fixed feature substitution in synthesis makefile
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2023-11-18 20:56:50 -08:00 |
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David Harris
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da6151a343
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Merge pull request #489 from ross144/main
fixes issue #487
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2023-11-18 19:22:33 -08:00 |
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Rose Thompson
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e3ab0fcc0a
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Merge pull request #488 from JacobPease/main
FPGA Bootloader Preload From File
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2023-11-18 17:24:52 -08:00 |
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Jacob Pease
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f8dbc94585
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Merge branch 'main' of github.com:openhwgroup/cvw
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2023-11-18 19:20:48 -06:00 |
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Jacob Pease
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16d8fa7ac9
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Updated ROM to preload bootloader from file and infer a block ram when building for FPGA.
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2023-11-18 19:15:39 -06:00 |
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Rose Thompson
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5ac659b73e
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-18 19:01:48 -06:00 |
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Rose Thompson
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8c5f13d2e8
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Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data.
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2023-11-18 19:01:39 -06:00 |
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Rose Thompson
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fba2a74098
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Merge pull request #485 from davidharrishmc/dev
Wally sweep running again, embench sweep across configs
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2023-11-17 21:42:12 -08:00 |
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David Harris
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cdc8a56b35
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turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep
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2023-11-17 20:25:24 -08:00 |
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David Harris
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8d2a1d93fd
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Restored RV64GC BPRED_SIZE=10 for consistent synthesis results
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2023-11-17 18:31:44 -08:00 |
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David Harris
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aceb620dce
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Ignore benchmark results
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2023-11-17 17:02:32 -08:00 |
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David Harris
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c8f9c4672a
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Embench Makefile to sweep experiments across configs
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2023-11-17 15:11:52 -08:00 |
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David Harris
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19e1a09681
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Got Wally sweep running again
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2023-11-17 15:10:57 -08:00 |
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David Harris
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296b9e6f7c
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-17 14:26:55 -08:00 |
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David Harris
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d54b97d307
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Merge pull request #480 from stineje/main
wrapper insertion automatically for Wally vs. individual PPA analysis
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2023-11-17 14:26:47 -08:00 |
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James E. Stine
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6c8341f59e
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Revert removal of WRAPPER option that is not prudent
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2023-11-17 16:25:35 -06:00 |
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David Harris
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0a39f40d49
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-17 13:28:07 -08:00 |
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David Harris
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d026b0e2bf
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Initial version of embench_arch_sweep.py
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2023-11-17 13:27:57 -08:00 |
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David Harris
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27e9ef1cac
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Merge pull request #484 from ross144/main
Changed bpred-sim.py to only simulate 12 jobs at once.
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2023-11-17 13:26:24 -08:00 |
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Rose Thompson
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8ddfdd44f6
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bpred-sim only simulates 12 jobs at once.
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2023-11-17 15:21:58 -06:00 |
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David Harris
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9d26fc9689
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Merge pull request #483 from ross144/main
Fixed branch predictor embench generation results
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2023-11-17 10:07:30 -08:00 |
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Rose Thompson
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889d685524
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Fixed bugs in paraseHPMC.py
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2023-11-17 12:05:22 -06:00 |
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Rose Thompson
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556fe16b0a
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Fixed testbench so it runs with BPRED_LOGGER but not PrintHPMCounters.
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2023-11-17 11:21:25 -06:00 |
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Jacob Pease
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93d217a40d
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ahbsdc submodule actually added this time.
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2023-11-16 17:46:48 -06:00 |
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Jacob Pease
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0aecc1ab75
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Deleted vivado-risc-v directory and added ahbsdc.
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2023-11-16 15:13:12 -06:00 |
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Jacob Pease
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e907cec4d3
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Merge branch 'main' of github.com:jacobpease/cvw
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2023-11-16 14:04:11 -06:00 |
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Jacob Pease
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402045b756
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Replaced vivado-risc-v addins directory with new SDC repo.
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2023-11-16 13:59:12 -06:00 |
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Rose Thompson
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b2184c6ac0
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Removed the size opt tests from the branch predictor analysis.
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2023-11-15 22:35:33 -06:00 |
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David Harris
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60be373cc2
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Merge pull request #481 from ross144/main
Fixed the BTB logger so sim_bp correctly reports BTB performance
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2023-11-15 17:45:38 -08:00 |
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Rose Thompson
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c6a24240f3
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Updates to btb logger processing.
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2023-11-15 16:53:44 -06:00 |
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Rose Thompson
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c2dc92b109
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Added btb reference data.
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2023-11-15 16:39:35 -06:00 |
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Rose Thompson
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809ac2203d
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Extended SeparateBranch to support both just branches and all control flow instructions.
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2023-11-15 16:36:49 -06:00 |
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Rose Thompson
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7df5d34bf4
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Fixed second bug in the logger script when branch logging enabled but counter logger not.
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2023-11-15 14:56:02 -06:00 |
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Rose Thompson
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15eddc8069
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Fixed bug in the btb branch logging.
We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.
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2023-11-15 14:51:47 -06:00 |
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David Harris
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b289e5275a
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changed to head of riscv-arch-test
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2023-11-15 09:48:13 -08:00 |
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