7 Commits

Author	SHA1	Message	Date
Jacob Pease	f1cc7dd5a3	Fixed verilog bugs.	2024-07-23 17:26:39 -05:00
Jacob Pease	a506d76149	Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.	2024-07-22 12:36:39 -05:00
Ross Thompson	ab1ee3d69b	Removed *** from IFU, lrcs.	2024-06-19 09:40:35 -07:00
Ross Thompson	c5dac4d775	Removed *** from fpga top.	2024-06-19 09:28:21 -07:00
Rose Thompson	7693c5d4e2	Updates to fpga top level.	2023-12-15 15:32:05 -06:00
Rose Thompson	26cd22c388	Replaced fpga's verilog top with system verilog.	2023-12-15 13:42:52 -06:00
Rose Thompson	dab9d7ab3c	Replaced fpga top level verilog with system verilog.	2023-12-15 13:07:08 -06:00