12 Commits

Author	SHA1	Message	Date
David Harris	f4957fdac1	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
Kevin	b928d01bb8	dot stars conversions on the rest of the testbenches	2021-12-12 17:53:26 -08:00
Ross Thompson	0f87f68b9d	Added either the sdModel or constant driver for the SDC ports in all test benches.	2021-09-24 12:31:51 -05:00
Ross Thompson	ef66cdeecf	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
David Harris	aef408af58	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
Thomas Fleming	d281ecd067	Remove imem from testbenches	2021-04-14 20:20:34 -04:00
ushakya22	ba01d57767	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
Teo Ene	80f6d6c944	Linux CoreMark is operational	2021-03-04 05:58:18 -06:00
Teo Ene	a82a123069	Implemented fix disucssed with Elizabeth	2021-03-03 18:17:53 -06:00
Teo Ene	d3a1afe50e	Fix to last push	2021-03-03 15:20:38 -06:00
Teo Ene	cfd45a46c3	Added provisional coremark files from work with Elizabeth	2021-02-24 20:07:07 -06:00
Teo Ene	5f84ed407c	Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts	2021-02-10 20:48:39 -06:00