Diego Herrera Vicioso
2d1806c5d0
Merge pull request #1 from dherreravicioso/AW_DH_privunit
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Added test coverage cases for writing to CSRs
2023-03-31 00:34:21 -07:00
David Harris
4069f4ba8d
Merge pull request #181 from kipmacsaigoren/bitmanip_cleanup
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Bitmanip cleanup
2023-03-30 19:23:54 -07:00
Kevin Kim
2c6359b097
only pass in relevant comparator flag to ALU
2023-03-30 19:15:33 -07:00
Kevin Kim
1e88ec7eac
Merge branch 'bitmanip_cleanup' of https://github.com/kipmacsaigoren/cvw into bitmanip_cleanup
2023-03-30 19:04:41 -07:00
Kevin Kim
27a5c9c5d6
Merge branch 'openhwgroup:main' into bitmanip_cleanup
2023-03-30 19:04:36 -07:00
Marcus Mellor
d4cb1a8582
Add comments to fpu.S indicating which lines of src/fpu/fctrl.sv are covered
2023-03-30 20:01:11 -05:00
Marcus Mellor
3afd963a9e
Disable coverage for branches tested in fpu.s
2023-03-30 19:44:55 -05:00
David Harris
da53f240d3
Refactored InstrValidNotFlushed into CSR Write signals
2023-03-30 17:06:09 -07:00
David Harris
406bb22b6a
Started factoring out InstrValidNotFlushed from CSRs
2023-03-30 14:56:19 -07:00
David Harris
f34218666a
fctrl updated and buildroot working again
2023-03-30 13:17:15 -07:00
David Harris
9129c3ac22
fctrl continued cleanup
2023-03-30 13:07:39 -07:00
David Harris
01c5d58a64
fctrl continued cleanup
2023-03-30 13:05:56 -07:00
David Harris
b2a102ce79
Started to clean up fctrl
2023-03-30 12:57:14 -07:00
Alec Vercruysse
4b58bb55f2
Make entire cache write path conditional on READ_ONLY_CACHE
2023-03-30 10:32:40 -07:00
David Harris
2924179424
Merge pull request #176 from kipmacsaigoren/priv-tests
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Fixed regression after cause CSR fix
2023-03-30 07:02:47 -07:00
Alessandro Maiuolo
9b290669d5
integrated tv generation for IFdivsqrt
2023-03-29 20:57:26 -07:00
Kip Macsai-Goren
3805cf993a
unnecessary comments cleanup
2023-03-29 19:32:57 -07:00
Kip Macsai-Goren
cfb236dd13
Merge branch 'priv-tests' of github.com:kipmacsaigoren/cvw into priv-tests
2023-03-29 16:31:35 -07:00
Kip Macsai-Goren
a7c9d3d37b
ported medelg fixes to 32 bit tests. Requires a make allclean
2023-03-29 16:31:28 -07:00
kipmacsaigoren
5cc1bc97da
Merge branch 'openhwgroup:main' into priv-tests
2023-03-29 15:34:47 -07:00
David Harris
6934a32747
Merge pull request #175 from SydRiley/main
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Starting IFU coverage expansion
2023-03-29 15:29:16 -07:00
Sydney Riley
4bd3121364
Manual merge in the coverage64gc
2023-03-29 15:25:27 -07:00
Kip Macsai-Goren
2e151b6b08
updated tests to reflect non-writeable bits of deleg
2023-03-29 15:24:00 -07:00
Sydney Riley
20fec0177d
Corrected authorship for IFU.S tests file
2023-03-29 15:20:46 -07:00
Sydney Riley
b0237eaa8b
Starting IFU tests including c.fld compressed instruction
2023-03-29 15:15:47 -07:00
Kip Macsai-Goren
491ef14b71
Resolved ImperasDV receiving incorrect cause values
2023-03-29 15:04:56 -07:00
Alec Vercruysse
d507f85190
icache coverage improvements by simplifying logic
2023-03-29 13:04:00 -07:00
Ross Thompson
5c4b753a1e
Merge pull request #173 from davidharrishmc/dev
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Test improvements including FPU coverage
2023-03-29 13:00:25 -05:00
David Harris
9d8f9e4428
Reduced number of bits in mcause and medeleg registers
2023-03-29 07:02:09 -07:00
David Harris
59f825a54b
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-29 06:19:10 -07:00
David Harris
d604a4fd33
Merge pull request #171 from AlecVercruysse/fix_152
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add check for legal funct3 for IW instructions
2023-03-29 06:18:31 -07:00
David Harris
d059da6eca
Turned on FS bit in fpu.S coverage test
2023-03-29 06:10:05 -07:00
Diego Herrera Vicioso
36d7ddf501
Added test coverage cases for writing to STVAL, SCAUSE, SEPC, and STIMECMP CSRs.
2023-03-28 22:48:17 -07:00
David Harris
115c042015
Turned off hpm counters
2023-03-28 21:28:56 -07:00
David Harris
f2c24b869d
Simplified fctrl
2023-03-28 21:13:48 -07:00
David Harris
3dc1c6673d
Started adding fpu fctrl tests
2023-03-28 21:13:25 -07:00
Alec Vercruysse
46df428e56
add check for legal funct3 for IW instructions
2023-03-28 15:59:48 -07:00
David Harris
92a7e86942
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-28 14:33:18 -07:00
David Harris
16742cbcb6
Merge pull request #170 from ross144/main
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Fixed issue 148 and problems with i/d cache address loggers.
2023-03-28 14:32:54 -07:00
Ross Thompson
d0f8db7939
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-28 16:31:50 -05:00
Ross Thompson
84860a062d
Modified the testbench to not use the loggers for unsupported configurations.
2023-03-28 16:27:54 -05:00
David Harris
6849eeae0c
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-28 14:27:08 -07:00
Ross Thompson
d33f4cfdef
Merge branch 'main' of github.com:ross144/cvw
2023-03-28 16:22:26 -05:00
Ross Thompson
c65c9e52d4
Disable loggers by default.
2023-03-28 16:20:45 -05:00
Ross Thompson
650a1a8d7e
Now reports if there is a hit or miss.
2023-03-28 16:20:14 -05:00
Ross Thompson
ef26600689
Restored performance counter reports.
2023-03-28 16:15:05 -05:00
Ross Thompson
a5601ea264
Now have logging of i/d cache addresses, but the performance counter reports are x's.
2023-03-28 16:09:54 -05:00
Ross Thompson
65d83b6f63
Merge branch 'main' of github.com:ross144/cvw
2023-03-28 14:47:16 -05:00
Ross Thompson
366a96a0fc
Possible fix for issue 148.
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I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.
I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.
This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
2023-03-28 14:47:08 -05:00
Kevin Kim
582c561cb1
comment formatting
2023-03-28 11:40:19 -07:00
