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9233 Commits

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Author SHA1 Message Date
David Harris
779458f14a Waive CBO failures in iterelf because ImperasDV does not handle them properly yet 2024-07-13 22:08:57 -07:00
David Harris
904a081218 allow wsim to take .elf in testsuite argument; print error if ELF not found 2024-07-13 21:59:26 -07:00
David Harris
26d4fbcc19 Switched ImperasDV to RV64GCK model to support crypto (issue #872) 2024-07-13 21:42:14 -07:00
Rose Thompson
35a3d2e43a Merge pull request #879 from JacobPease/main 
main
 2024-07-12 09:32:13 -05:00
Jacob Pease
7f72fb8583 Updated riscv,isa-extensions property with the correct syntax. Added riscv,cbom-block-size. 2024-07-12 09:28:54 -05:00
Jordan Carlin
a4967138b6
Merge pull request #875 from ross144/main 2024-07-11 18:05:14 -07:00
Rose Thompson
82bd9ca200 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-07-11 11:32:12 -05:00
Rose Thompson
8f52e4ae42
Merge pull request #878 from JacobPease/main 
Commented out riscv,isa-extensions from Arty device tree until Linux kernel is updated.
 2024-07-11 11:25:24 -05:00
Jacob Pease
1a2607c3d9 Commented out riscv,isa-extensions from Arty device tree until Linux kernel is updated. 2024-07-11 10:53:18 -05:00
Ross Thompson
c72f0fd504 Added csr comparison. 2024-07-11 10:49:06 -05:00
Ross Thompson
abf9da01ab code cleanup. 2024-07-11 10:41:34 -05:00
Ross Thompson
f0096f5a43 Yay. It's actually working! The FPGA/ImperasDV hybrid is working. 2024-07-10 15:10:37 -05:00
Ross Thompson
e6dc962d11 Yay! the trigger is correctly working now! 2024-07-10 12:05:10 -05:00
Ross Thompson
cf986b5fb8 Really close to having the trigger in module work. 
Can trigger on the data of the correct frame, but trigger in is still not
working.
 2024-07-09 19:04:51 -05:00
Ross Thompson
6734685333 Fixed connection bugs in the top level fpga which preventing sending ethernet frames back to the trigger in unit. 2024-07-09 19:04:18 -05:00
Ross Thompson
e0a1f0e39f Really close now. 2024-07-09 14:21:43 -05:00
Ross Thompson
e488ee7225 Correctly sending the ethernet frame on a mismatch. Now just need to get vivado to actually trigger. 2024-07-09 14:16:13 -05:00
Ross Thompson
fd170a6583 Getting closer. 2024-07-09 14:09:56 -05:00
Ross Thompson
bf69a2e1cd Updated to use the newest imperasDV. 2024-07-09 12:30:18 -05:00
Rose Thompson
f83e6cf771 Fixed issue #874. 2024-07-08 14:48:52 -05:00
Jordan Carlin
43b9e2ca92 Refactor section headers 2024-07-08 07:21:08 -07:00
Jordan Carlin
ae1829f23a Cleanup 2024-07-08 06:50:29 -07:00
Jordan Carlin
2528830e98 Merge remote-tracking branch 'upstream/main' into installation 
Fix derivgen.pl shebang conflict
 2024-07-08 06:46:41 -07:00
Rose Thompson
15b23ceb4d
Merge pull request #866 from davidharrishmc/dev 
First version of iterelf running; removed directory support from wsim
 2024-07-07 10:27:22 -05:00
David Harris
9098a55ea3 Fixed lint error in imperas derived config 2024-07-06 05:36:12 -07:00
David Harris
bcbe9eec81 Added lockstep simulations for coverage, wally-riscv-arch-test, buildroot boot to nightly / buildroot regression 2024-07-05 22:13:34 -07:00
David Harris
84c687080d Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-07-05 21:42:26 -07:00
David Harris
9f5e7b8653
Merge pull request #851 from kevindkim723/intdivb 
Reduce Bit widths for IDIV on FPU
 2024-07-05 21:42:19 -07:00
David Harris
02a7a1696b git ignore 2024-07-05 21:35:10 -07:00
David Harris
ffb248dc65 Fixed issue 868 about tlbmisc.S coverage test failing due to HPTW writing wrong address when updateing A bit 2024-07-05 21:32:57 -07:00
David Harris
9279b2d56a Added imperas configuration for Lee 2024-07-05 09:13:18 -07:00
David Harris
ced8038343 Defined memory to be inaccessible by default 2024-07-05 08:34:28 -07:00
Jordan Carlin
2217fa0794 Fix setup.csh typo 2024-07-04 13:45:24 -07:00
Jordan Carlin
f0268a011a Add comments to site-setup for new gcc 2024-07-04 13:44:50 -07:00
David Harris
604f9d3a45 Fixed imperas.ic prefix for vcs 2024-07-04 12:31:00 -07:00
David Harris
873bd61296 Fixed perl path in derivgen 2024-07-04 12:30:11 -07:00
David Harris
12717a65f2 Fixed location of imperas.ic with new misa_B_Zba_Zbb_Zbs 2024-07-04 12:29:59 -07:00
David Harris
775930ae4f Fixes to memfile generation for rv32. Updated new misa.B in imperas.ic, but need new version of ImperasDV to test 2024-07-04 07:36:56 -07:00
Jordan Carlin
83449c16ab Fix perl shebang lines 2024-07-04 01:48:20 -07:00
Jordan Carlin
8991931bef Update run_vcs shebang after merge 2024-07-03 23:47:26 -07:00
Jordan Carlin
838e44a53f Merge branch 'main' of https://github.com/openhwgroup/cvw into installation 2024-07-03 23:44:25 -07:00
Jordan Carlin
9f52f7712a Update installation script comments 2024-07-03 23:42:31 -07:00
Jordan Carlin
6f71f30a42 Add error messages 2024-07-03 22:26:10 -07:00
Jordan Carlin
65b3a97379 Speed up qemu clone with multiple submodules in parallel 2024-07-03 22:14:17 -07:00
Jordan Carlin
e5c82e7465 Additional shebang updates 2024-07-03 21:34:48 -07:00
Jordan Carlin
e6e070f4e4 Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability) 2024-07-03 20:42:55 -07:00
Jordan Carlin
01bce0c0b8 Update README with new installation flow and other general cleanup 2024-07-03 19:51:52 -07:00
David Harris
8645441d00 Testbench automatically creates memfile, label, addr files if they are out of date or missing 2024-07-03 16:52:16 -07:00
David Harris
9b120bb3aa fix timeout in iterelf 2024-07-03 16:34:14 -07:00
David Harris
4528b4ee2a Fix wsim to use absolute path for ELF 2024-07-03 15:10:02 -07:00