Harshini Srinath
0c324bce7b
Update prioritythermometer.sv
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Program clean up
2023-06-11 19:18:21 -07:00
Harshini Srinath
66856f31ca
Update or_rows.sv
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Program clean up
2023-06-11 19:16:37 -07:00
Harshini Srinath
250ea7668e
Update neg.sv
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Program clean up
2023-06-11 19:15:28 -07:00
Harshini Srinath
5a40272fd7
Update counter.sv
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Program clean up
2023-06-11 19:12:57 -07:00
Harshini Srinath
16028a5766
Update adder.sv
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Program clean up
2023-06-11 19:09:18 -07:00
Ross Thompson
30e3d2cdce
Merge pull request #233 from AlecVercruysse/coverage3
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Full I$ coverage
2023-04-14 22:15:11 -05:00
Alec Vercruysse
4d9aa72877
replace instances of code duplication for i$ exclusions w/commands
2023-04-14 17:10:39 -07:00
Limnanthes Serafini
49e025bd48
Final small fix
2023-04-14 14:15:52 -07:00
Limnanthes Serafini
2c20079a46
indent fix
2023-04-14 14:14:34 -07:00
Limnanthes Serafini
b3976daccd
More cleanup
2023-04-13 21:34:50 -07:00
Ross Thompson
81074a822a
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-04-09 12:19:44 -05:00
David Harris
7affe2bdca
Waived coverage on BTB memory with byte write enables tied high
2023-04-07 21:56:49 -07:00
Ross Thompson
07b946bc75
Fixed syntax error.
2023-04-06 15:10:55 -05:00
Ross Thompson
4407d3310c
Added note about strange vivado behavior not inferring block ram.
2023-04-06 15:09:35 -05:00
Ross Thompson
ee4cf5e94d
Similifed the no byte write enabled version of the sram model.
2023-04-06 14:18:41 -05:00
Alec Vercruysse
ac3569d75c
Update ram1p1rwe (ce & we) coverage exlusion explanation
2023-04-05 14:54:58 -07:00
Alec Vercruysse
782feb6161
turn off ce coverage for ram1p1rwe
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According to the textbook, the cache memory chip enable,
`CacheEn`, is only lowered by the cachefsm with it is in the ready
state and a pipeline stall is asserted.
For read only caches, cache writes only occur in the state_write_line
state. So there is no way that a write would happen while the chip
enable is low.
Removing the chip-enable check from this memory to increase coverage
would be a bad idea since if anyone else uses this ram, the behaviour
would be differently than expected. Instead, I opted to turn off
coverage for this statement. Since this ram, which does not have a
byte enable, is used exclusively by read-only caches right now, this
should not mistakenly exclude coverage for other cases, such as D$.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
8b6b96012d
add ram1p1rwe for read-only cache ways (remove byte-enable)
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- increases coverage
2023-04-05 11:48:18 -07:00
Ross Thompson
46b1bca4fc
Fixed all tap/space issue in RTL.
2023-03-24 17:32:25 -05:00
David Harris
4e1bf6fbe0
Improved IEU and bitmanip test coverage
2023-03-23 14:24:41 -07:00
David Harris
36b2d530c4
Merge pull request #98 from ross144/main
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New gshare implementation
2023-02-20 11:27:47 -08:00
David Harris
4cc8448b16
Removed unused and incomplete ROM macro instantations
2023-02-20 05:59:57 -08:00
Ross Thompson
407d9e7b4a
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-02-19 22:54:27 -06:00
David Harris
527566c38a
Fixed RAM instantiations
2023-02-19 06:31:41 -08:00
David Harris
154d7eb9ef
Fixed RAM bugs and refactored with read taking place after clock edge rather than before.
2023-02-17 19:14:38 -08:00
David Harris
daf2f822c2
Memory synthesis updates
2023-02-17 15:33:49 -08:00
David Harris
3f2f48ddc6
Continue fixing memory macros for synthesis
2023-02-17 15:15:37 -08:00
David Harris
aba29f6cc8
Synthesis with memories
2023-02-17 13:51:05 -08:00
Ross Thompson
b62bacbac3
keep this commit off of cvw.
2023-02-16 11:05:24 -06:00
James Stine
a3aeff2703
Update if-then-else for ram items
2023-02-15 18:12:12 -06:00
Kevin Kim
2dfbf15ff9
fixed typo in LZC
2023-02-11 19:59:03 -08:00
David Harris
e6bfcd14fa
Merged with memories
2023-02-02 14:50:46 -08:00
David Harris
78eb90715c
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
