Ross Thompson
0b3dc288ec
Made furture progress in the mmu tests.
2021-07-16 15:56:06 -05:00
Ross Thompson
6521d2b468
Also changed the shadow ram's dcache copy widths.
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Merge branch 'dcache' into main
2021-07-16 14:21:09 -05:00
Ross Thompson
46bce70e42
Fixed walker fault interaction with dcache.
2021-07-16 12:22:13 -05:00
Ross Thompson
e0f719d513
Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
2021-07-16 11:12:57 -05:00
Kip Macsai-Goren
abd5b1c02d
Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.
2021-07-15 18:30:29 -04:00
Ross Thompson
e5d624c1fa
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
2021-07-15 11:56:35 -05:00
Ross Thompson
fa26aec588
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Ross Thompson
b9902b0560
Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
2021-07-15 11:00:42 -05:00
Ross Thompson
8610ef204c
Renamed DCacheStall to LSUStall in hart and hazard.
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Added missing logic in lsu.
2021-07-15 10:16:16 -05:00
Ross Thompson
704f4f724e
dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.
2021-07-14 23:08:07 -05:00
Ross Thompson
ba1e1ec231
Finally have the ptw correctly walking through the dcache to update the itlb.
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Still not working fully.
2021-07-14 22:26:07 -05:00
Katherine Parry
c74d26eea4
Fixed lint warning
2021-07-14 21:24:48 -04:00
Ross Thompson
c79650b508
Added d cache StallW checks for any time the cache wants to go to STATE_READY.
2021-07-14 17:25:50 -05:00
Ross Thompson
2c946a282f
Fixed d cache not honoring StallW for uncache writes and reads.
2021-07-14 17:23:28 -05:00
Katherine Parry
f5bfdf46db
fpu unpacking unit created
2021-07-14 17:56:49 -04:00
Ross Thompson
e91501985c
Routed CommittedM and PendingInterruptM through the lsu arb.
2021-07-14 16:18:09 -05:00
Ross Thompson
adce800041
Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled.
2021-07-14 15:47:38 -05:00
Ross Thompson
d78e31e9df
Forgot to include one hot decoder.
2021-07-14 15:46:52 -05:00
Ross Thompson
f4295ff097
Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
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This solves the committedM issue.
2021-07-14 15:00:33 -05:00
James Stine
e6d19be87c
put back for now to test fdiv
2021-07-14 06:48:29 -05:00
Ross Thompson
9b756d6a94
Implemented uncached reads.
2021-07-13 23:03:09 -05:00
Ross Thompson
e8bf502bc2
Added CommitedM to data cache output.
2021-07-13 22:43:42 -05:00
Ross Thompson
3e57c899a2
Partially working changes to support uncached memory access. Not sure what CommitedM is.
2021-07-13 17:24:59 -05:00
James E. Stine
46001fef27
mod 2 of fpdivsqrt update
2021-07-13 16:59:17 -04:00
James E. Stine
8382a17969
Update fpdivsqrt item until move into uarch
2021-07-13 16:53:20 -04:00
Ross Thompson
baa2b5d15f
Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled.
2021-07-13 14:51:42 -05:00
Ross Thompson
3c1a717399
Fixed the fetch buffer accidental overwrite on eviction.
2021-07-13 14:21:29 -05:00
Ross Thompson
32f27cfecf
Dcache AHB address generation was wrong. Needed to zero the offset.
2021-07-13 14:19:04 -05:00
Ross Thompson
afc1bc9c38
Moved StoreStall into the hazard unit instead of in the d cache.
2021-07-13 13:20:50 -05:00
David Harris
9de97c1e20
Fixed busybear by restoring InstrValidW needed by testbench
2021-07-13 14:17:36 -04:00
Ross Thompson
47e16f5629
Fixed back to back store issue.
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Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
2021-07-13 12:46:20 -05:00
David Harris
2ba82d1a5c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 13:26:51 -04:00
David Harris
223086ac33
added or.sv
2021-07-13 13:26:40 -04:00
Katherine Parry
ca19b2e215
Fixed writting MStatus FS bits
2021-07-13 13:22:04 -04:00
Katherine Parry
efdec72df1
Fixed writting MStatus FS bits
2021-07-13 13:20:30 -04:00
David Harris
b5dddec858
Fixed InstrValid from W to M stage for CSR performance counters
2021-07-13 13:19:13 -04:00
Ross Thompson
224e3b2991
Fixed subword write. subword read should not feed into subword write.
2021-07-13 11:21:44 -05:00
David Harris
861ef5e1cb
Replaced .or with or_rows structural code in MMU read circuitry for synthesis.
2021-07-13 09:32:02 -04:00
Ross Thompson
49f6eec579
Team work on solving the dcache data inconsistency problem.
2021-07-12 23:46:32 -05:00
Ross Thompson
1cc258ade1
Progress towards the test bench flush.
2021-07-12 14:22:13 -05:00
Katherine Parry
f3ac46df86
fcvt.sv cleanup
2021-07-11 21:30:01 -04:00
Katherine Parry
36f59f3c99
Almost all convert instructions pass Imperas tests
2021-07-11 18:06:33 -04:00
Ross Thompson
f26d635614
Fixed the spurious AHB requests to address 0. Somehow by not having a default
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(else) in the fsm branch selection for STATE_READY in the d cache it was
possible to take an invalid branch through the fsm.
2021-07-10 22:34:47 -05:00
Ross Thompson
fed7042fd9
Loads are working.
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There is a bug when the icache stalls 1 cycle before the d cache.
2021-07-10 22:15:44 -05:00
Ross Thompson
60ed023734
Actually writes the correct data now on stores.
2021-07-10 17:48:47 -05:00
Ross Thompson
efe37ea079
Write miss with eviction works.
2021-07-10 15:17:40 -05:00
Ross Thompson
d65c01bc29
Write Hits and Write Misses without eviction are working correctly! The next
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step is to add eviction of dirty lines.
2021-07-10 10:56:25 -05:00
David Harris
d3ab6b192a
added missing tlbmixer.sv
2021-07-09 19:18:23 -04:00
Ross Thompson
b1ceeb40df
Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address.
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I think this is do to the cycle latency of stores. We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a
full cache block or a word write from the CPU.
2021-07-09 17:14:54 -05:00
Ross Thompson
4c0cee1c19
Design loads in modelsim, but trap is an X.
2021-07-09 15:37:16 -05:00
