Commit Graph

7470 Commits

Author SHA1 Message Date
Rose Thompson
09b04fca35 Disable the trace for normal operation. 2023-11-21 13:49:07 -06:00
Rose Thompson
2a2d24c701 Output the instruction trace to the logs directory. 2023-11-21 13:47:58 -06:00
Rose Thompson
274c18976f Merge branch 'main' of github.com:ross144/cvw 2023-11-21 13:46:45 -06:00
Rose Thompson
989a74b203 Updated qemu scripts for updated linux build.
expanded memory from 128MB to 256MB.
2023-11-21 13:46:37 -06:00
Rose Thompson
42c3555d8c Finally we got the wally tracer working with linux. 2023-11-21 13:45:55 -06:00
Rose Thompson
82d53fdef9 We are logging now. 2023-11-21 13:02:34 -06:00
Rose Thompson
666ccc1413 Added code to the wallyTracer to support outputing an instruction trace. 2023-11-21 12:28:19 -06:00
Rose Thompson
0e876293a2 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-11-21 10:48:05 -06:00
Rose Thompson
17b9b17d86 Merge branch 'main' of github.com:ross144/cvw 2023-11-21 10:40:01 -06:00
Rose Thompson
95580d9093
Merge pull request #493 from stineje/main
marchid approved by RISC-V
2023-11-21 08:33:07 -08:00
Rose Thompson
a7683a48cd
Merge pull request #492 from davidharrishmc/dev
Clean up unused signals, other cleanup
2023-11-21 08:32:19 -08:00
James E. Stine
dfd8f2d0c1 Update ppaAnalyze for recent update to put back parsing name 2023-11-21 09:24:07 -06:00
James E. Stine
5c5b956b0f Update marchid/mvendorid for CV-Wally 2023-11-21 09:23:02 -06:00
David Harris
d26c505a4d repo cleanup and start to add CMO tests 2023-11-20 23:41:36 -08:00
David Harris
b9023af535 Removed other unused signals from Verilog 2023-11-20 23:37:56 -08:00
David Harris
b0f118a93a removed unused cache signals 2023-11-20 23:16:35 -08:00
Rose Thompson
cababf9840 More simplifications. 2023-11-21 00:19:24 -06:00
Rose Thompson
25e217ee03 More cleanup. 2023-11-21 00:14:59 -06:00
Rose Thompson
89e62e9fee cleanup. 2023-11-20 23:59:40 -06:00
Rose Thompson
2757c03c7e More optimizations to simplify cmo logic. 2023-11-20 22:13:31 -06:00
Rose Thompson
60c79ea88c Removed the CMO_WRITEBACK state from the cache and unused signals. 2023-11-20 20:56:30 -06:00
Rose Thompson
75c5510216 Removed the CMO_WRITEBACK state from the cache. 2023-11-20 20:52:11 -06:00
Rose Thompson
b75bb5ab02 Simplified CMO.Zero fsm implementation slightly. 2023-11-20 17:01:43 -06:00
David Harris
f7fb30573f
Merge pull request #491 from ross144/main
Running ImperasDV Linux is upto date
2023-11-20 10:28:05 -08:00
Rose Thompson
7d467462d4 Merge branch 'main' of github.com:ross144/cvw 2023-11-20 11:29:45 -06:00
Rose Thompson
d4865505b4 Finally have the cbo way muxing controls reduced to something sane. 2023-11-20 11:28:03 -06:00
Rose Thompson
199a84eee0 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-11-20 10:34:36 -06:00
Rose Thompson
aa6ee8ecdc Merge branch 'main' of github.com:ross144/cvw 2023-11-20 10:30:42 -06:00
Rose Thompson
bc41f12195 Modified linux imperas tests to
1. enable zicclsm
2. enable logging at 7000 ms
2023-11-20 10:30:35 -06:00
Rose Thompson
baf9546a73
Merge pull request #490 from davidharrishmc/dev
Synthesis running for textbook, preload IROM to avoid it being optimized out, updated M tests in risk-arch-test
2023-11-19 20:42:29 -08:00
David Harris
65a09a81e9 Commented IROM preloading 2023-11-19 19:33:57 -08:00
Rose Thompson
be672a0770 Added menvcfg to debugger for checking what linux has configured. 2023-11-19 13:44:22 -06:00
David Harris
b549c95bfd Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-19 06:49:25 -08:00
David Harris
9d3da4d1da wallySynthAll.sh automates running all synthesis experiments without maxopt 2023-11-19 06:49:07 -08:00
David Harris
1b9c93e07a Changed rv32gc to do IDIV in MDU and have k=2 copies of FDIV stages; added correct sky130 adder data; fixed feature substitution in synthesis makefile 2023-11-18 20:56:50 -08:00
David Harris
da6151a343
Merge pull request #489 from ross144/main
fixes issue #487
2023-11-18 19:22:33 -08:00
Rose Thompson
e3ab0fcc0a
Merge pull request #488 from JacobPease/main
FPGA Bootloader Preload From File
2023-11-18 17:24:52 -08:00
Jacob Pease
f8dbc94585 Merge branch 'main' of github.com:openhwgroup/cvw 2023-11-18 19:20:48 -06:00
Jacob Pease
16d8fa7ac9 Updated ROM to preload bootloader from file and infer a block ram when building for FPGA. 2023-11-18 19:15:39 -06:00
Rose Thompson
5ac659b73e Merge branch 'main' of github.com:ross144/cvw 2023-11-18 19:01:48 -06:00
Rose Thompson
8c5f13d2e8 Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data. 2023-11-18 19:01:39 -06:00
Rose Thompson
fba2a74098
Merge pull request #485 from davidharrishmc/dev
Wally sweep running again, embench sweep across configs
2023-11-17 21:42:12 -08:00
David Harris
cdc8a56b35 turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep 2023-11-17 20:25:24 -08:00
David Harris
8d2a1d93fd Restored RV64GC BPRED_SIZE=10 for consistent synthesis results 2023-11-17 18:31:44 -08:00
David Harris
aceb620dce Ignore benchmark results 2023-11-17 17:02:32 -08:00
David Harris
c8f9c4672a Embench Makefile to sweep experiments across configs 2023-11-17 15:11:52 -08:00
David Harris
19e1a09681 Got Wally sweep running again 2023-11-17 15:10:57 -08:00
David Harris
296b9e6f7c Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-17 14:26:55 -08:00
David Harris
d54b97d307
Merge pull request #480 from stineje/main
wrapper insertion automatically for Wally vs. individual PPA analysis
2023-11-17 14:26:47 -08:00
James E. Stine
6c8341f59e Revert removal of WRAPPER option that is not prudent 2023-11-17 16:25:35 -06:00