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Author SHA1 Message Date
bbracker
099fc34c10 change genTrace to dump UART output to file so we can see how far parsing got 2022-03-08 09:52:17 -08:00
bbracker
742e8d98cd fix up PLIC and UART checkpointing 2022-03-07 23:48:47 -08:00
bbracker
bfaf496473 change UART state saving to temporarily modify LCR so that DLAB=0 when reading addresses 0 and 1 so that we get RBR and IER instead of divisor latch registers 2022-03-07 22:12:08 -08:00
bbracker
92e1583db5 change testbench-linux.sv to use new shared location of disassembly files 2022-03-07 20:04:08 -08:00
bbracker
097301635a change checkpoint generation to integrate GDB scripting more cleanly and save UART and PLIC state 2022-03-07 17:59:49 -08:00
bbracker
409dd48706 modify debug.sh to not rely on external GDB script 2022-03-07 11:56:04 -08:00
bbracker
4bf95714eb add debug.sh 2022-03-07 19:52:19 +00:00
Shreya Sanghai
c15517d334 removed reminant changes 2022-03-07 17:36:05 +00:00
Shreya Sanghai
a218a3d9fa undid changes to synth script 2022-03-07 17:32:08 +00:00
Shreya Sanghai
94a57fb6eb modified synth script to take config from outputdir 2022-03-07 17:12:43 +00:00
Shreya Sanghai
bc049e8042 updated makefile to speed up synth 2022-03-07 00:09:18 +00:00
Shreya Sanghai
a68c1c8cb1 modified makefile 2022-03-07 00:09:18 +00:00
bbracker
483aad2a05 update checkpointSweep in accordance to having removed trace parsing feature 2022-03-06 14:55:51 -08:00
bbracker
bea2faeda6 remove vestigial silencePipe mechanism 2022-03-06 14:54:35 -08:00
bbracker
11e9bbf3e4 needed to initialize checkpoint directory 2022-03-06 14:51:25 -08:00
bbracker
d007208aa9 no longer use cythonization on python parser scripts because its a little complicated and has marginal benefit 2022-03-06 14:40:26 -08:00
bbracker
f64b7776ed give genCheckpoint the same de-sudo'ing treatement 2022-03-06 14:37:12 -08:00
bbracker
7182ec228f better to use $tvDir variable rather than abs path 2022-03-06 14:33:53 -08:00
bbracker
8f2e67984f replace sudo's with suggestions in genRecording.sh 2022-03-06 14:31:55 -08:00
bbracker
e57b5208dc replace sudo's in genTrace.sh with suggested commands 2022-03-06 14:24:50 -08:00
bbracker
91f327e109 small bugfix to suggested sudo commands for linux testvectors 2022-03-06 14:16:23 -08:00
bbracker
742b9d884d remove checkpoint trace generation since that requires qemu hacking and because we are able to generate the whole trace on VLSI 2022-03-06 14:04:30 -08:00
bbracker
bb90644fb2 add path to Modelsim on vlsi 2022-03-06 13:55:19 -08:00
bbracker
e3f735cc1a recommend sudo commands without automatically executing them in genInitMem.sh 2022-03-06 13:30:19 -08:00
bbracker
efee8d3a22 change from clang to gcc when compiling testvector-generation executables 2022-03-06 13:18:53 -08:00
bbracker
b1120069a0 generate $WALLY in a way that works for bash and zsh 2022-03-06 13:12:20 -08:00
bbracker
70ddc98d19 Revert "fix "dirname: missing operand" bug from setup.sh" 
This reverts commit 60cbd1c9c1.
 2022-03-06 12:48:53 -08:00
David Harris
db3b253ac1 Fixed merge of fpcalc 2022-03-06 13:32:13 +00:00
David Harris
7391c6d338 Checked in fma16_template.v 2022-03-06 13:29:35 +00:00
bbracker
1fc7856c36 add extractFunctionRadix step to buildroot Makefile 2022-03-05 19:02:07 -08:00
bbracker
4eb46785fc change genInitMem.sh to check for sufficient directory privileges rather than invoke sudo 2022-03-05 18:04:00 -08:00
bbracker
891ec82d81 remove linux-testgen dir because it is now completely obsolete 2022-03-05 17:26:30 -08:00
bbracker
60cbd1c9c1 fix "dirname: missing operand" bug from setup.sh 2022-03-05 17:21:34 -08:00
David Harris
e6133f3d83 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-04 07:21:22 -08:00
David Harris
bffd417567 Cleaned up printing and warnings in fpcalc.c 2022-03-04 07:21:18 -08:00
David Harris
cba6f10c19 Prettied up softfloat_demo 2022-03-04 05:16:20 +00:00
David Harris
99a0e2d73d Adjusted scripts to use 2022-03-04 05:09:02 +00:00
David Harris
c13517f0ce Defined WALLY in setup as pointer to repository 2022-03-03 21:00:07 -08:00
David Harris
e4d18f1808 removed more old 64priv tests 2022-03-04 03:57:19 +00:00
bbracker
41c75dc89d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:12:00 +00:00
bbracker
c3e59ae2df comment out nonfunctioning CSR-PERMISSIONS-M test 2022-03-04 00:11:55 +00:00
David Harris
a50f1a4424 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:07:34 +00:00
David Harris
2cea3349ad LSU/Cache code review notes 2022-03-04 00:07:31 +00:00
bbracker
d645666fe7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:06:27 +00:00
bbracker
79ff8d3c80 remove imperas32p tests 2022-03-04 00:06:18 +00:00
David Harris
db7d3cfc0e Updated Makefile to reflect new Linux and Imperas situation. Updated setup to include Synopsys license file. 2022-03-03 11:28:22 -08:00
David Harris
6431ad4a8b Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas 2022-03-03 15:38:08 +00:00
David Harris
f76e396255 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-02 23:47:16 +00:00
David Harris
8e83aaeced fma file fixes 2022-03-02 23:47:01 +00:00
bbracker
87aad1d953 fix peripheral test and add it to regression 2022-03-02 23:44:39 +00:00