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Author	SHA1	Message	Date
Ross Thompson	313bc5255c	Improved address bus names and usages in the walker, dcache, and tlbs. ... Merge branch 'walkerEnhance' into main	2021-07-21 14:55:09 -05:00
Ross Thompson	310b454fa1	Added comment about better muxing.	2021-07-21 14:40:14 -05:00
Ross Thompson	5860f147d4	4 way set associative is now working.	2021-07-21 14:01:14 -05:00
Kip Macsai-Goren	1c1ae2d61e	removed remaining 32 bit loads/stores with 64 bit ones.	2021-07-21 14:45:22 -04:00
Kip Macsai-Goren	4eaf95de60	Fixed TLB parameterization and valid bit flop to correctly do instr page faults	2021-07-21 14:44:43 -04:00
Katherine Parry	01f0b4e5df	FDIV and FSQRT work	2021-07-21 14:08:14 -04:00
bbracker	f9c0d33773	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-21 13:04:11 -04:00
bbracker	82ce85c24f	progress on recovering from QEMU's errors	2021-07-21 13:00:32 -04:00
Ross Thompson	e0990535e1	Fixed remaining bugs in 2 way set associative dcache.	2021-07-21 10:35:23 -05:00
Ross Thompson	3f780f012a	Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux. ... Also forgot to include cacheLRU.sv file.	2021-07-20 23:17:42 -05:00
Katherine Parry	b9081e514c	FMA parameterized	2021-07-20 22:04:21 -04:00
Kip Macsai-Goren	2cdb019602	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 21:04:53 -04:00
Kip Macsai-Goren	1f4718192c	light cleanup	2021-07-20 20:49:07 -04:00
Kip Macsai-Goren	656c1c9949	added new execution tests that should work with dcache memory non-syncness with 'real memory'. They make, but don't pass regression yet	2021-07-20 20:47:20 -04:00
Kip Macsai-Goren	bac10a2198	added new executable test, cheange PTE to test library	2021-07-20 20:39:00 -04:00
Ross Thompson	14e949d6e3	Partially working 2 way set associative d cache.	2021-07-20 17:51:42 -05:00
bbracker	f9b6bd91f5	fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk	2021-07-20 17:55:44 -04:00
Kip Macsai-Goren	7e83fdff19	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 17:01:09 -04:00
bbracker	a02694a529	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 15:04:13 -04:00
bbracker	a3823ce3a9	commented out old hack that used hardcoded addresses	2021-07-20 15:03:55 -04:00
David Harris	e5e3f5abe6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 14:46:58 -04:00
David Harris	1f3dfa20f6	flag for optional boottim	2021-07-20 14:46:37 -04:00
Ross Thompson	4c785845f3	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-20 13:27:58 -05:00
Ross Thompson	00081ebc68	Replaced FinalReadDataM with ReadDataM in dcache.	2021-07-20 13:27:29 -05:00
Abe	89dc9ba6e4	Updated riscv64-unknown-elf-gcc location so that it can be easily accessed	2021-07-20 14:18:13 -04:00
bbracker	6b72b1f859	ignore mhpmcounters because QEMU doesn't implement them	2021-07-20 13:37:52 -04:00
Kip Macsai-Goren	93ea2000dc	Updated MMU tests to use shared library in assembly	2021-07-20 12:35:30 -04:00
bbracker	a1ea654b11	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 12:08:46 -04:00
David Harris	e1a1a8395e	Parameterized I$/D$ configurations and added sanity check assertions in testbench	2021-07-20 08:57:13 -04:00
bbracker	077662bfa1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 05:40:49 -04:00
bbracker	9e658466e6	testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)	2021-07-20 05:40:39 -04:00
James E. Stine	12e09a7ace	slight mod to fpdiv - still bug in batch vs. non-batch	2021-07-20 01:47:46 -04:00
bbracker	3b10ea9785	major fixes to CSR checking	2021-07-20 00:22:07 -04:00
Ross Thompson	365485bd8b	Added performance counters for dcache access and dcache miss.	2021-07-19 22:12:20 -05:00
Ross Thompson	508c3e35af	Restored TIM range.	2021-07-19 21:17:31 -05:00
bbracker	99fa2bbbc3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 19:30:40 -04:00
bbracker	cb15d7e4c7	change debugBuildroot because GDB formatted list is now 50 lines long per instruction (we lost 6 CSRs on the whole)	2021-07-19 19:30:29 -04:00
David Harris	23b76a724d	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 18:19:59 -04:00
David Harris	4d40b5faef	Added cache configuration to config files	2021-07-19 18:19:46 -04:00
bbracker	c1d63fe77c	MemRWM shouldn't factor into PCD checking	2021-07-19 18:03:30 -04:00
bbracker	4d10cfc98b	create qemu_output.txt	2021-07-19 18:02:41 -04:00
bbracker	c8203c171e	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 17:11:49 -04:00
bbracker	f7d040af1e	make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways	2021-07-19 17:11:42 -04:00
Kip Macsai-Goren	5880cbafe4	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 16:46:46 -04:00
bbracker	1aeef4e7d1	remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux	2021-07-19 16:22:05 -04:00
bbracker	bc5222e721	put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests	2021-07-19 16:19:24 -04:00
bbracker	f17f6cea56	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 15:42:26 -04:00
bbracker	65df5c087b	adapt testbench to removal of ReadDataWEn signal	2021-07-19 15:42:14 -04:00
bbracker	ae5663a244	adapt testbench to removal of signal	2021-07-19 15:41:50 -04:00
bbracker	64e0fe4c5a	whoops MTIMECMP is always 64 bits	2021-07-19 15:40:53 -04:00