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0678e70b4b
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408 Commits

Author SHA1 Message Date
Ross Thompson
0678e70b4b Merge branch 'imperas' 2023-01-31 12:46:22 -06:00
Ross Thompson
20e99dce73 Fixed parameterization in testbench. 2023-01-31 00:11:01 -06:00
Ross Thompson
b64b3016e2 Parameterized testbench branch predictor preload. 2023-01-31 00:08:11 -06:00
Ross Thompson
7a4218788c Imperas found a real bug in virtual memory. 
If the instruction address spilled across two pages and the second page misses the TLB,
the HPTW received a tlb miss at the address of the first page rather than the second.
After the walk the TLB was updated with the PTE from the first page at the address of the
second page.

Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
 2023-01-30 11:47:51 -06:00
Ross Thompson
a9902337cf Merge branch 'main' of https://github.com/openhwgroup/cvw 
This merges the branch predictor improvements into the main repo.
 2023-01-29 15:24:20 -06:00
Ross Thompson
244885d3fa Found bug in gshare. 2023-01-29 15:03:25 -06:00
Ross Thompson
49a7d10914 Fixed typo in testbench branch logger. 2023-01-29 01:00:52 -06:00
Ross Thompson
5c83de4c46 Fixed another bug with the branch logger. 2023-01-29 00:59:59 -06:00
Ross Thompson
6afd7f4fac Fixed bug in the branch logger. 2023-01-29 00:58:50 -06:00
Ross Thompson
250a8df7c3 Updated testbench for branch logger. 2023-01-29 00:56:11 -06:00
David Harris
b89fe9989e Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED 2023-01-28 18:52:00 -08:00
David Harris
fa3643a064 Renamed BUS to BUS_SUPPORTED 2023-01-28 18:35:53 -08:00
David Harris
8a96dcf0ae Config cleanup and renamed BPRED_ENABLED to BPRED_SUPPORTED 2023-01-28 18:17:42 -08:00
Ross Thompson
684a7214cb Added another performance counter to track overall branch miss-predictions. 2023-01-28 17:50:46 -06:00
David Harris
a99fc74976 Removed integer from localparams 2023-01-27 14:40:06 -08:00
David Harris
b173112f86 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
Ross Thompson
f1049be6c1 More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
11c44006c4 Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
eroom1966
8dea3491a3 Partial fix for misaligned LD/ST 2023-01-18 17:11:39 +00:00
eroom1966
0ccab9accc changes made with Ross 2023-01-18 16:46:48 +00:00
eroom1966
52ebac59b8 remove volatile for FFLAGS and FCSR 2023-01-18 13:33:57 +00:00
Ross Thompson
374f95ebf3 Fixed the rvvi CSR write enable not synchronized with a valid instruction in the Writeback stage. 2023-01-17 18:24:46 -06:00
Ross Thompson
8f5b5e0989 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-17 15:44:44 -06:00
David Harris
fd52915f3c Clean up warnings from Questa 2023-01-17 13:43:39 -08:00
Ross Thompson
b2676e1dd4 Somehow the imperas files spilled into the main branch. 2023-01-17 15:39:34 -06:00
eroom1966
cf3223df22 refactor all rvvi into single initial block 2023-01-17 13:01:01 +00:00
eroom1966
2ead2cdaf4 Code refactor and addition of rvvi interface 2023-01-17 12:47:38 +00:00
Ross Thompson
7984194c2a Fixed issue with rvvi tracer so it reports call csr changes, not just instrutions which write the CSRs. 2023-01-16 13:35:06 -06:00
David Harris
53d0d28828 csr cleanup 2023-01-13 22:12:06 -08:00
David Harris
c5358da771 csr cleanup 2023-01-13 21:25:55 -08:00
Ross Thompson
4a73018d6e Merge branch 'rastemp' 2023-01-13 18:09:50 -06:00
Ross Thompson
b26cec1ef4 Possible optimization of gshare. 
I don't believe the Writeback stage ghr is needed.
 2023-01-13 12:39:29 -06:00
Ross Thompson
14ecaabbf6 Nearly complete RVVI tracer. 
Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
 2023-01-12 18:43:39 -06:00
Ross Thompson
59b135d895 Added supervisor mode registers to tracer. 2023-01-12 17:04:41 -06:00
Ross Thompson
6500321aaf Added M CSRs to the CSRArray. 2023-01-12 16:51:51 -06:00
Ross Thompson
8981739310 added machine csr to logger. 2023-01-12 16:35:19 -06:00
Ross Thompson
f3443e2eca Added support to print the gprs. 2023-01-12 16:09:30 -06:00
Ross Thompson
0ea0e7a9e1 rvvi trace is coming alone nicely. 2023-01-12 14:46:31 -06:00
Ross Thompson
9a180f88f7 Completely stripped down imperas simulation. 
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
 2023-01-12 12:48:38 -06:00
Ross Thompson
5112ffcbc9 Stripped out all signature checking. 
Removed multiple tests loop.
Only runs 1 test now.
 2023-01-12 12:45:44 -06:00
Ross Thompson
8ee80c5d54 Created separate imperas testbench. 
Resolved logger issue with the duplicated instructions after commit.
 2023-01-12 12:07:07 -06:00
Ross Thompson
f59e1d03fc Added instruction logger. 2023-01-12 10:09:34 -06:00
Katherine Parry
4079f76a78 cleaned up all FPU files except for division 2023-01-11 22:02:30 -06:00
Ross Thompson
e3df1d3326 Restored to default configuration. 2023-01-09 00:21:45 -06:00
Ross Thompson
f643b45b97 Added branch outcome logger to testbench 2023-01-07 13:16:57 -06:00
Ross Thompson
48cf8d58b4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-06 15:18:13 -06:00
Ross Thompson
81fe08192e Added python script to post process performance counter metrics. 2023-01-06 15:15:54 -06:00
Ross Thompson
cd17d296d2 Added code to print out performance counters at end of each test. 2023-01-05 18:00:11 -06:00
Ross Thompson
f8c656f1e0 Simiplified global history branch predictor. 2023-01-04 23:41:55 -06:00
Katherine Parry
fd3b967496 some commenting fixes, converter optimizations, and moves normshift into postproc 2023-01-03 15:55:30 -06:00