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54 Commits

Author SHA1 Message Date
Ross Thompson
cc51a27a34 Fixed bug with flush dirty not cleared in the correct cache line. 2022-01-05 14:14:01 -06:00
David Harris
da5ead23bf Removed more generate statements 2022-01-05 16:01:03 +00:00
Ross Thompson
98be8201b2 Renamed most signals inside cache.sv so they are agnostic to i or d. 2022-01-04 23:52:42 -06:00
Ross Thompson
fffaf654e6 the i and d caches now share common verilog. 2022-01-04 23:40:37 -06:00