Ross Thompson
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583d87afc7
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Change CurrPtr to Ptr in RAS.
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2023-02-03 17:40:20 -06:00 |
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Kevin Kim
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202c45bef2
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Merge branch 'main' of https://github.com/kipmacsaigoren/cvw
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2023-02-03 18:39:26 +00:00 |
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Kevin Kim
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9c3f062f4d
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arch32ba includes the 32i_m tests instead of 64
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2023-02-03 17:40:02 +00:00 |
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Kip Macsai-Goren
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fc549d1595
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Merge remote-tracking branch 'upstream/main' into main
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2023-02-03 09:31:06 -08:00 |
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David Harris
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34fbfeb5cd
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Removed redundant line from synthesis makefile
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2023-02-03 08:36:51 -08:00 |
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David Harris
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97ee3732fe
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-02-03 08:36:11 -08:00 |
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David Harris
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4dca69f205
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Updated division radix test script with paths, but script is out of date for files it manipulates
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2023-02-03 08:36:03 -08:00 |
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Kevin Kim
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3d67e48bef
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Merge branch 'main' of https://github.com/kipmacsaigoren/cvw
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2023-02-03 16:00:36 +00:00 |
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Kevin Kim
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d47a44a62f
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ALU changes (ZBB)
- handles inverted operand instructions
- handles shift-and-add instructions
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2023-02-03 16:00:32 +00:00 |
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David Harris
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1763de52ea
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Merge pull request #54 from ross144/main
Fixed issue #50, itlb and dcache flush interlock
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2023-02-03 06:30:30 -08:00 |
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Ross Thompson
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4547da80ea
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Fixed bug #49.
FFLAGS was updated while the pipeline was stalled.
Also I found serveral performance counters which had similar issues.
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2023-02-03 00:39:26 -06:00 |
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Ross Thompson
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659b511616
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Lee Moore found another bug using imperas.
An ITLB miss concurrent with a d cache flush did not interlock.
The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
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2023-02-02 23:52:21 -06:00 |
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Kevin Kim
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a0adcf6a85
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Merge branch 'openhwgroup:main' into main
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2023-02-02 21:41:55 -08:00 |
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Kevin Kim
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f0730c13e2
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Started Zbb
-Performs byte instructions (orc.b, rev8 (32/64))
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2023-02-03 05:40:38 +00:00 |
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Kevin Kim
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a0ea436b9c
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zbs minor lint fix
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2023-02-03 05:31:50 +00:00 |
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Kevin Kim
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44e5a7e913
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zbc initial done; passes lint.
clmul logic changes have not verified yet
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2023-02-03 04:48:23 +00:00 |
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David Harris
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644dfe7463
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Removed lab1matrix solutions
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2023-02-02 19:40:41 -08:00 |
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Kevin Kim
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adc96ecaaa
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added bit reverse module, passes lint
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2023-02-02 23:10:57 +00:00 |
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David Harris
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e6bfcd14fa
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Merged with memories
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2023-02-02 14:50:46 -08:00 |
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David Harris
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80f42a8638
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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David Harris
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78eb90715c
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Removed pipelined level of hierarchy
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2023-02-02 14:14:11 -08:00 |
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David Harris
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3531afa5cf
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Update README.md
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2023-02-02 12:59:28 -08:00 |
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Kevin Kim
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e2228f6341
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started zbc
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2023-02-02 20:11:11 +00:00 |
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Kevin Kim
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aadc1de746
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zbs passes lint
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2023-02-02 20:04:38 +00:00 |
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James E. Stine
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4b2a13bc44
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Merge pull request #52 from stineje/main
Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22
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2023-02-02 13:55:17 -06:00 |
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James Stine
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924e55325c
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Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22
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2023-02-02 13:54:25 -06:00 |
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Kevin Kim
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ae5d7844a9
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clmul finished initial hdl; passes lint
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2023-02-02 19:49:14 +00:00 |
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David Harris
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e4f2e96449
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Merge pull request #51 from stineje/main
Modify generic/mem for rv32gc ram2
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2023-02-02 11:41:32 -08:00 |
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James Stine
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9a5023a17e
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Modify generic/mem for rv32gc ram2
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2023-02-02 13:28:18 -06:00 |
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Kevin Kim
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f07ffbb63b
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continued clmul unit
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2023-02-02 18:54:33 +00:00 |
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David Harris
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30ba42d498
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-02-02 10:28:40 -08:00 |
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Kevin Kim
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bd8f0189ee
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started clmul
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2023-02-02 16:40:58 +00:00 |
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David Harris
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0af2ff969c
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Merge pull request #48 from ross144/main
Fixed bug #47, ecall and ebreak don't commit
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2023-02-02 06:58:07 -08:00 |
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Ross Thompson
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3c8f07ffa1
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Merge branch 'main' of github.com:ross144/cvw
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2023-02-02 08:52:48 -06:00 |
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Ross Thompson
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3838ab232b
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Fixed bug #47 discovered by Lee Moore.
ECALL and EBREAK do not commit their results.
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2023-02-02 08:52:06 -06:00 |
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Ross Thompson
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7f207527ce
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Merge branch 'main' of https://github.com/openhwgroup/cvw into main
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2023-02-02 08:48:19 -06:00 |
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Kip Macsai-Goren
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0281330fe8
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Merge remote-tracking branch 'upstream/main' into main
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2023-02-01 21:31:57 -08:00 |
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Kip Macsai-Goren
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f126d1e0ef
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added beginning of a ZBS instruction module to the ALU. Control signals still needed
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2023-02-01 21:31:25 -08:00 |
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Ross Thompson
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279c62c402
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-02-01 19:24:10 -06:00 |
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David Harris
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0a540495f6
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Removed O2 from fir Makefile to be consistent with lab.
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2023-02-01 15:43:52 -08:00 |
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David Harris
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c5578cc2fb
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Merge pull request #45 from stineje/main
Update ram2 and other memories and associated wrappers
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2023-02-01 15:06:30 -08:00 |
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James Stine
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fc5692629a
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Update ram2 and other memories and associated wrappers
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2023-02-01 17:03:48 -06:00 |
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Ross Thompson
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3276353b8c
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Minor branch predictor bug fix.
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2023-02-01 10:59:38 -06:00 |
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Ross Thompson
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51a2a71410
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Removed unused signal.
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2023-02-01 10:27:58 -06:00 |
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David Harris
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8601f04397
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Fixed typo in DC setup for memories
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2023-02-01 05:49:30 -08:00 |
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David Harris
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e820d1938a
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Only add memory libraries when targeting 28nm
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2023-02-01 05:06:56 -08:00 |
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David Harris
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733b877f1d
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Merge pull request #36 from davidharrishmc/dev
RV32imc configuration
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2023-02-01 04:44:36 -08:00 |
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David Harris
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ce82d8d550
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Fixed merge conflict to get synthesis working again
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2023-02-01 04:43:57 -08:00 |
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David Harris
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39942bbc45
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Merge pull request #43 from mmasserfrye/main
ram size, bpred size, memories *SYNTH NOT FUNCTIONAL*
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2023-02-01 04:13:37 -08:00 |
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Ross Thompson
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6fb624950e
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Minor change to btb.
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2023-02-01 00:24:54 -06:00 |
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