Ross Thompson
d62cd1f701
Reverted changes to subwordread while keeping the new names of the i/o.
2021-12-28 15:57:21 -06:00
Ross Thompson
9c190b019b
Name changes for states in LSU.
2021-12-28 15:03:24 -06:00
Ross Thompson
13b4201198
Added generate around virtual memory hardware in LSU.
2021-12-28 15:00:02 -06:00
Ross Thompson
f09b10a393
Moved generate for lrsc to lsu.
2021-12-28 14:17:18 -06:00
Ross Thompson
73af458eb5
More cleanup of dcache.
2021-12-28 14:12:18 -06:00
Ross Thompson
0e86e5d9f1
Additional cleanup of the LSU.
2021-12-28 13:59:07 -06:00
Ross Thompson
1e76c24f26
Major cleanup of the LSU.
2021-12-28 13:10:45 -06:00
Ross Thompson
79b17c5b55
Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
2021-12-28 12:33:07 -06:00
Ross Thompson
34c11ca8d5
Minor dcache cleanup.
2021-12-28 11:29:16 -06:00
Ross Thompson
243728d089
Moved all bus logic outside the dcache. Still needs cleanup.
2021-12-28 11:18:47 -06:00
Ross Thompson
74d636cb53
First cut at moving the dcache bus interface into the LSU.
...
Regression test does not run and there is a lot of cleanup to do.
2021-12-27 18:12:59 -06:00
Ross Thompson
d366a1f50f
Moved dcache fetch logic outside the dcache except for the fsm.
2021-12-27 16:45:49 -06:00
Ross Thompson
e3ddcbb11e
Partial commit.
...
Moved AMO, SWW, and SWR outside the dcache.
Step 1 of separate the fetching logic from the caches.
2021-12-27 15:56:18 -06:00
David Harris
66ad7ddf1c
Added D and F tests to regression
2021-12-27 04:35:34 +00:00
David Harris
67d5b1bb42
Fixed exe2memfile.pl bug
2021-12-27 00:44:18 +00:00
David Harris
6e20d011d5
Fixed imperas C tests
2021-12-26 04:45:06 +00:00
David Harris
e6ed1372a7
Incorporated new Imperas tests. f and d tests are failing and c tests are hanging.
2021-12-26 04:36:53 +00:00
David Harris
48bb534658
Started FIR test code and started incorporating Imperas tests
2021-12-25 22:39:51 +00:00
David Harris
d9e61fad67
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-25 06:37:30 -08:00
David Harris
9b491788b2
Checked in Chapter 2 C and assembly examples
2021-12-25 06:35:36 -08:00
Ross Thompson
d9977aa1f1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-23 12:40:42 -06:00
Ross Thompson
7fe70c3cc6
Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages.
...
1: It simplifies the interactions between the caches and the hptw.
2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process.
There are two downsides.
1: Pollute the TLBs with not very relavent translations
2: Have to compute the misalignment. This can be cached in the TLB which only costs 1 flip flop
for each TLB line.
2021-12-23 12:40:22 -06:00
David Harris
a8c72c08a9
added wallyVirtIO.patch from Ross
2021-12-22 07:04:47 -08:00
Ross Thompson
4e1ae8c71f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-21 22:38:05 -06:00
Ross Thompson
f863bdc495
linux-wave.do changes.
2021-12-21 22:37:55 -06:00
David Harris
9ab7c18baa
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-22 03:59:14 +00:00
David Harris
b15707bb84
Fixed directory in Makefile for exe2memfile
2021-12-22 03:59:08 +00:00
Ross Thompson
6a8e917e06
It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register.
2021-12-21 15:59:56 -06:00
Ross Thompson
7844d3f064
Fixed bug where the wrong address is read into the icache memory.
2021-12-21 15:16:00 -06:00
Ross Thompson
8b97aaac3e
Fixed complex bug where FENCE is instruction class miss predicted as a taken branch.
2021-12-21 11:29:28 -06:00
Ross Thompson
3f62a64056
Identified bug in the IFU which selects PCNextF when InvalidateICacheM is true. If the ID is invalid PCNextF should NOT be PCE.
2021-12-20 23:45:55 -06:00
Ross Thompson
a157235a4b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 23:27:46 -06:00
Ross Thompson
ffe792bcfc
Fixed bug on icache spill. if the cpu stalled on the completion it was possible to use the wrong address for the sram read. Also miss spill hit always selected the wrong address.
2021-12-20 23:27:37 -06:00
David Harris
b085339303
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-20 21:16:25 -08:00
David Harris
07810f4025
Renamed to setup.sh and fixed path bug
2021-12-20 21:14:35 -08:00
David Harris
e00791a890
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-21 05:10:17 +00:00
David Harris
09a24f7240
Improving Wally installation makefile
2021-12-21 05:10:14 +00:00
David Harris
bf9082b0ad
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-20 21:09:20 -08:00
David Harris
475fa01767
Fixing paths in wally-setup.sh
2021-12-20 21:08:34 -08:00
Ross Thompson
6acf6257e4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 21:26:48 -06:00
Ross Thompson
50b307bc0e
Looks like rdtime was accidentally replaced with rrame from a find and replace.
2021-12-20 21:26:38 -06:00
David Harris
972841717f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-21 02:35:45 +00:00
David Harris
787af4287e
Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead
2021-12-21 02:35:41 +00:00
Ross Thompson
8416cae3fe
Fixed Type 5b interaction between dcache and hptw.
...
This is a load concurrent with ITLBMiss.
2021-12-20 18:33:31 -06:00
Ross Thompson
b6d75d453a
Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM.
2021-12-20 10:03:56 -06:00
Ross Thompson
beb1988539
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
Ross Thompson
df8bd78679
More signal name cleanup in LSU.
2021-12-19 22:47:48 -06:00
Ross Thompson
3eb5f33705
Remove verbosity from lsu state machine.
2021-12-19 22:41:34 -06:00
Ross Thompson
d3c3422d12
Rename of SelPTW to SelHPTW.
2021-12-19 22:24:07 -06:00
Ross Thompson
8feb36b926
Signal renames.
2021-12-19 22:21:03 -06:00
