David Harris
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c74fec7fa6
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renamed sim-fp to sim-testfloat
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2022-06-02 15:05:29 -07:00 |
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Katherine Parry
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21f7d16005
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added create all vectores file
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2022-06-02 21:56:47 +00:00 |
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Katherine Parry
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03280c0f9c
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added createallvectors
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2022-06-02 21:56:05 +00:00 |
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David Harris
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0195178a79
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-02 20:50:56 +00:00 |
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Katherine Parry
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f573f9d17b
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removed fp vectors
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2022-06-02 20:50:32 +00:00 |
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David Harris
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4c702fa03c
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Reverted fp testcase ignore
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2022-06-02 20:50:23 +00:00 |
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David Harris
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bb30c90eeb
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-02 20:48:34 +00:00 |
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David Harris
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ed7d6d4c28
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mulAdd tests in gitignore
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2022-06-02 20:48:14 +00:00 |
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Katherine Parry
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94867e3b14
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added testvectors fp
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2022-06-02 20:48:10 +00:00 |
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slmnemo
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c8515001a2
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-02 12:54:08 -07:00 |
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Katherine Parry
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9a09ee3a35
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fpu paramaterized - except fdivsqrt
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2022-06-02 19:50:28 +00:00 |
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slmnemo
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88454aa2ab
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Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do"
This reverts commit 89c7438424.
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2022-06-02 12:45:21 -07:00 |
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slmnemo
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ad9e85beb9
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Revert "Fixed buildroot by adding a second ."
This reverts commit 8b27c1884e.
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2022-06-02 12:43:59 -07:00 |
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slmnemo
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65b8d0c32a
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Revert "Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py"
This reverts commit e33ca59d46.
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2022-06-02 12:41:01 -07:00 |
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slmnemo
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0d650b2880
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Revert "Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace"
This reverts commit e4024eb503.
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2022-06-02 12:40:46 -07:00 |
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David Harris
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1d8bc2dc1b
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Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit
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2022-06-02 09:37:59 -07:00 |
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David Harris
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154410a37f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-02 15:48:36 +00:00 |
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David Harris
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faa15b1f8d
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Cleaned up comments in controller
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2022-06-02 15:48:33 +00:00 |
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David Harris
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197b588193
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Cleaned up test cases in testbench
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2022-06-02 08:44:28 -07:00 |
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David Harris
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c7ec9282fe
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Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
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2022-06-02 14:18:55 +00:00 |
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slmnemo
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c16c5beef5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-02 02:52:03 +00:00 |
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slmnemo
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65961223f8
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Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files
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2022-06-02 02:51:51 +00:00 |
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Katherine Parry
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e42afbfb30
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paramerterized some small fma units
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2022-06-01 23:34:29 +00:00 |
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Madeleine Masser-Frye
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30f4a7e37b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-01 21:02:55 +00:00 |
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Madeleine Masser-Frye
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bed4fad7b2
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fixed errors in synth.out by switching ( to {
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2022-06-01 21:02:49 +00:00 |
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DTowersM
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215f69a2ab
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-01 21:00:51 +00:00 |
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DTowersM
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d28b4cf602
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added support for embench post processing to testbench.sv
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2022-06-01 21:00:44 +00:00 |
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DTowersM
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ee7070c5b6
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some changes to further support vsim on embench
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2022-06-01 17:19:19 +00:00 |
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Katherine Parry
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dd19e55b8f
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unpacker optimizations
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2022-06-01 16:52:21 +00:00 |
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slmnemo
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446ad498aa
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Fixed double assignment on LSUBurstType
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2022-06-01 01:04:49 +00:00 |
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cturek
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949f53695d
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Fixed typos
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2022-06-01 00:07:36 +00:00 |
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slmnemo
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cf05fec9c7
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Added signals to change HTRANS to the correct signal based on schematic as well as a way to tell if we are not on the first access
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2022-05-31 16:33:05 -07:00 |
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slmnemo
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a86c4d5ff3
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Merge branch 'cacheburstmode' of github.com:davidharrishmc/riscv-wally into cacheburstmode
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2022-05-31 15:57:55 -07:00 |
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slmnemo
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9ad1a42886
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Redid the FSM to prepare for burst mode implementation
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2022-05-31 15:57:42 -07:00 |
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David Harris
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475a84491e
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Unpackinput cleanup
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2022-05-31 22:31:21 +00:00 |
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David Harris
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f9533fea1a
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Removed normalized output from unpack and simplified interface
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2022-05-31 21:32:31 +00:00 |
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David Harris
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0d0a9cba66
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-31 21:12:45 +00:00 |
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David Harris
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aa7b0616e4
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../src/privileged/csrc.sv
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2022-05-31 21:12:17 +00:00 |
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DTowersM
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8903af3764
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-31 20:13:41 +00:00 |
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DTowersM
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525f6a6069
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added testbench.sv support for embench tests, test output still WIP
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2022-05-31 20:13:32 +00:00 |
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DTowersM
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0de54a01bf
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removed delapidated signals SIE_REGW SIP_REGW TimerIntM SwIntM
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2022-05-31 20:10:56 +00:00 |
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DTowersM
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95df88ae70
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added embench tests to tests.vh
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2022-05-31 20:08:04 +00:00 |
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DTowersM
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ae12cca980
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dummy start trigger and stop trigger support for make file
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2022-05-31 20:05:51 +00:00 |
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Katherine Parry
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f6ac33ce8a
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reorginized unpackinput signals
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2022-05-31 17:40:34 +00:00 |
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Katherine Parry
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4ed7933aa3
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added unpackinput.sv
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2022-05-31 16:18:50 +00:00 |
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David Harris
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1e1555891f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-31 14:58:18 +00:00 |
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David Harris
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788fe406b5
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Moved delegation logic from privmode to trap to simplify interface
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2022-05-31 14:58:11 +00:00 |
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Madeleine Masser-Frye
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887090dbae
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plots saved to synthDC/plots instead of shown
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2022-05-30 19:56:47 +00:00 |
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Madeleine Masser-Frye
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8506d98bec
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added optimized area plotting
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2022-05-30 18:54:02 +00:00 |
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David Harris
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0cfe9e3373
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Removed unused fp add and convert modules
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2022-05-29 23:07:56 +00:00 |
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