Ross Thompson
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42fe5ceee3
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Cleaned up icache and dcache.
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2021-07-22 11:06:44 -05:00 |
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Ross Thompson
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6abd23a61d
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Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
Also faults and the dcache ptw interlock are not implemented.
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2021-07-09 15:16:38 -05:00 |
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Ross Thompson
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4c5aee3042
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This d cache fsm is getting complex.
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2021-07-08 15:26:16 -05:00 |
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David Harris
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d2e3e14cbc
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-04 18:55:24 -04:00 |
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David Harris
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57e1111df3
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Gave names to for loops in generate blocks for ease of reference
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2021-07-04 18:52:16 -04:00 |
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bbracker
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11606e96f1
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ICacheCntrl now reacts differently to InstrPageFaultF vs ITLBWriteF
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2021-07-04 18:17:06 -04:00 |
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Ben Bracker
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66692af57c
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src/cache/ICacheCntrl.sv
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2021-07-03 11:24:41 -05:00 |
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Ben Bracker
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d6c7dc02ed
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fix ICache indenting
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2021-07-03 11:11:07 -05:00 |
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Ross Thompson
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3dae02818c
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OMG. It's working!
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2021-07-01 17:37:53 -05:00 |
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Ross Thompson
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4530e43df6
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The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay.
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2021-06-30 17:02:36 -05:00 |
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Ross Thompson
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2598f08782
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Page table walker now walks the table.
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
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2021-06-29 22:33:57 -05:00 |
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Ross Thompson
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d5063bee7d
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Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
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2021-06-23 15:13:56 -05:00 |
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Ross Thompson
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03084a4128
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Icache now uses physical lenght bits rather than XLEN.
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2021-06-21 16:41:09 -05:00 |
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Ross Thompson
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8ec5b0c4f1
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Improved some names in icache.
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2021-06-21 16:40:37 -05:00 |
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Ross Thompson
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bb756849a7
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Revert "Icache now uses physical lenght bits rather than XLEN."
This reverts commit d4de8a54a2.
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2021-06-19 08:58:34 -05:00 |
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Ross Thompson
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e4c932265d
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Revert "Improved some names in icache."
This reverts commit 22ea801edb.
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2021-06-19 08:58:32 -05:00 |
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Ross Thompson
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22ea801edb
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Improved some names in icache.
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2021-06-18 12:22:41 -05:00 |
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Ross Thompson
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d4de8a54a2
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Icache now uses physical lenght bits rather than XLEN.
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2021-06-18 12:02:59 -05:00 |
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David Harris
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5e01f71c52
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disabled Verilator WIDTH warnings in ICCacheCntrl
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2021-06-12 19:50:06 -04:00 |
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David Harris
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e231fc6b00
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More verilator fixes, but bpred is broken
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2021-06-09 21:03:03 -04:00 |
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Ross Thompson
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e200b4b5a4
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Continued I-Cache cleanup.
Removed strange mux on InstrRawD along with
the select logic.
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2021-06-04 15:14:05 -05:00 |
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Ross Thompson
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2c16591396
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Reorganized the icache names.
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2021-06-04 12:53:42 -05:00 |
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