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Added integer step counter to fsm

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This commit is contained in:
cturek 2022-11-11 00:23:25 +00:00
parent d5c5450f8d
commit ff410cd849
2 changed files with 5 additions and 3 deletions
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2
pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
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@ -74,7 +74,7 @@ module fdivsqrt(
fdivsqrtfsm fdivsqrtfsm( fdivsqrtfsm fdivsqrtfsm(
.clk, .reset, .FmtE, .XsE, .SqrtE, .clk, .reset, .FmtE, .XsE, .SqrtE,
.DivBusy, .DivStartE,.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .DivBusy, .DivStartE,.StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
.XNaNE, .YNaNE, .XNaNE, .YNaNE, .MDUE, .n,
.XInfE, .YInfE, .WZero, .SpecialCaseM); .XInfE, .YInfE, .WZero, .SpecialCaseM);
fdivsqrtiter fdivsqrtiter( fdivsqrtiter fdivsqrtiter(
.clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM, .clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM,

6
pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
View File

@ -42,7 +42,9 @@ module fdivsqrtfsm(
input logic SqrtE, input logic SqrtE,
input logic StallE, input logic StallE,
input logic StallM, input logic StallM,
input logic WZero, input logic WZero,
input logic MDUE,
input logic [`DIVBLEN:0] n,
output logic DivDone, output logic DivDone,
output logic DivBusy, output logic DivBusy,
output logic SpecialCaseM output logic SpecialCaseM
@ -93,7 +95,7 @@ module fdivsqrtfsm(
always_comb begin always_comb begin
if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); cycles = MDUE ? n : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
end end
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */