From ff410cd849f3f1374a53b6c8a511e97d877d0cd5 Mon Sep 17 00:00:00 2001 From: cturek Date: Fri, 11 Nov 2022 00:23:25 +0000 Subject: [PATCH] Added integer step counter to fsm --- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index 3f9c7e8a5..65ea6cc54 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -74,7 +74,7 @@ module fdivsqrt( fdivsqrtfsm fdivsqrtfsm( .clk, .reset, .FmtE, .XsE, .SqrtE, .DivBusy, .DivStartE,.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, - .XNaNE, .YNaNE, + .XNaNE, .YNaNE, .MDUE, .n, .XInfE, .YInfE, .WZero, .SpecialCaseM); fdivsqrtiter fdivsqrtiter( .clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM, diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 8dc188c6b..94a19ed3a 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -42,7 +42,9 @@ module fdivsqrtfsm( input logic SqrtE, input logic StallE, input logic StallM, - input logic WZero, + input logic WZero, + input logic MDUE, + input logic [`DIVBLEN:0] n, output logic DivDone, output logic DivBusy, output logic SpecialCaseM @@ -93,7 +95,7 @@ module fdivsqrtfsm( always_comb begin if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs - cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); + cycles = MDUE ? n : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); end /* verilator lint_on WIDTH */