From ff409d4fe7938e847614240d09fba2e47de2e0c4 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 23 Oct 2021 08:39:21 -0700
Subject: [PATCH] Lint cleanup

---
 .../src/cache/cachereplacementpolicy.sv       |  6 ++---
 wally-pipelined/src/muldiv/intdivrestoring.sv | 16 ++++++------
 wally-pipelined/src/muldiv/redundantmul.sv    | 25 +++++++++++++------
 3 files changed, 28 insertions(+), 19 deletions(-)

diff --git a/wally-pipelined/src/cache/cachereplacementpolicy.sv b/wally-pipelined/src/cache/cachereplacementpolicy.sv
index 01d225b1c..fa115586a 100644
--- a/wally-pipelined/src/cache/cachereplacementpolicy.sv
+++ b/wally-pipelined/src/cache/cachereplacementpolicy.sv
@@ -46,11 +46,11 @@ module cachereplacementpolicy
   always_ff @(posedge clk, posedge reset) begin
     if (reset) begin
       for(int index = 0; index < NUMLINES; index++)
-	      ReplacementBits[index] = '0;
+	      ReplacementBits[index] <= '0;
     end else begin
-      BlockReplacementBits = ReplacementBits[RAdr];
+      BlockReplacementBits <= ReplacementBits[RAdr];
       if (LRUWriteEn) begin
-	      ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] = NewReplacement;
+	      ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement;
       end
     end
   end
diff --git a/wally-pipelined/src/muldiv/intdivrestoring.sv b/wally-pipelined/src/muldiv/intdivrestoring.sv
index cf0d5341b..dd92c9692 100644
--- a/wally-pipelined/src/muldiv/intdivrestoring.sv
+++ b/wally-pipelined/src/muldiv/intdivrestoring.sv
@@ -115,19 +115,19 @@ module intdivrestoring (
 
  always_ff @(posedge clk) 
     if (reset) begin
-        state = IDLE; 
+        state <= IDLE; 
     end else if (DivStartE) begin 
-        step = 0;
-        if (Div0E) state = DONE;
-        else       state = BUSY;
+        step <= 1;
+        if (Div0E) state <= DONE;
+        else       state <= BUSY;
      end else if (state == BUSY) begin // pause one cycle at beginning of signed operations for absolute value
-        step = step + 1;
         if (step[STEPBITS] | (`XLEN==64) & W64E & step[STEPBITS-1]) begin // complete in half the time for W-type instructions
-            state = DONE;
+            state <= DONE;
         end
+        step <= step + 1;
     end else if (state == DONE) begin
-      if (StallM) state = DONE;
-      else        state = IDLE;
+      if (StallM) state <= DONE;
+      else        state <= IDLE;
     end 
 endmodule 
 
diff --git a/wally-pipelined/src/muldiv/redundantmul.sv b/wally-pipelined/src/muldiv/redundantmul.sv
index 9c8ade60a..70fdc8b57 100644
--- a/wally-pipelined/src/muldiv/redundantmul.sv
+++ b/wally-pipelined/src/muldiv/redundantmul.sv
@@ -4,7 +4,15 @@
 // Written: David_Harris@hmc.edu and ssanghai@hm.edu 10/11/2021
 // Modified: 
 //
-// Purpose: redundant multiplier 
+// Purpose: multiplier with output in redundant carry-sum form
+//          This can be faster than a mutiplier that requires a final adder to obtain the nonredundant answer.
+//          The module has several implementations controlled by the DESIGN_COMPILER flag.
+//          When DESIGN_COMPILER = 1, use the Synopsys DesignWare DW02_multp block.  This will give highest quality results
+//                                    but doesn't work in simulation or when using different tools
+//          When DESIGN_COMPILER = 2, use the Wally mult_cs block with Radix 2 Booth encoding and a Wallace Tree
+//                                    This simulates and synthesizes, but quality of results ae lower than DesignWare
+//          Otherwise, just use a nonredundant multiplier and set one word to 0.  This is best for FPGAs, which have
+//                                    block multipliers, and also simulates fastest.
 // 
 // A component of the Wally configurable RISC-V project.
 // 
@@ -29,18 +37,19 @@ module redundantmul #(parameter WIDTH =8)(
   input logic [WIDTH-1:0]    a,b,
   output logic [2*WIDTH-1:0] out0, out1);
 
-   logic [2*WIDTH-1+2:0]     tmp_out0;
-   logic [2*WIDTH-1+2:0]     tmp_out1;   
+  // 
 
    generate
-      if (`DESIGN_COMPILER == 1)
+      if (`DESIGN_COMPILER == 1) 
 	begin
-	   DW02_multp #(WIDTH, WIDTH, 2*WIDTH+2) mul(.a, .b, .tc(1'b0), .out0(tmp_out0), .out1(tmp_out1));
-	   assign out0 = tmp_out0[2*WIDTH-1:0];
-	   assign out1 = tmp_out1[2*WIDTH-1:0];
+        logic [2*WIDTH-1+2:0]     tmp_out0; // DW02_
+        logic [2*WIDTH-1+2:0]     tmp_out1;   
+	  DW02_multp #(WIDTH, WIDTH, 2*WIDTH+2) mul(.a, .b, .tc(1'b0), .out0(tmp_out0), .out1(tmp_out1));
+	  assign out0 = tmp_out0[2*WIDTH-1:0];
+	  assign out1 = tmp_out1[2*WIDTH-1:0];
 	end
       else if (`DESIGN_COMPILER == 2)
-	mult_cs #(WIDTH) mul(.a, .b, .tc(1'b0), .sum(out0), .carry(out1));
+	  mult_cs #(WIDTH) mul(.a, .b, .tc(1'b0), .sum(out0), .carry(out1));
       else begin // force a nonredunant multipler.  This will simulate properly and also is appropriate for FPGAs.
 	 assign out0 = a * b;
 	 assign out1 = 0;