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Make cache output NOP after a reset

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This commit is contained in:
Jarred Allen 2021-03-25 13:18:30 -04:00
parent fdecd6c56c
commit feabcf2d50
4 changed files with 6 additions and 6 deletions
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2
wally-pipelined/regression/wave-dos/ahb-waves.do
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@ -4,7 +4,7 @@ add wave -divider
#add wave /testbench/dut/hart/ebu/IReadF #add wave /testbench/dut/hart/ebu/IReadF
add wave /testbench/dut/hart/DataStall add wave /testbench/dut/hart/DataStall
add wave /testbench/dut/hart/InstrStall add wave /testbench/dut/hart/ICacheStallF
add wave /testbench/dut/hart/StallF add wave /testbench/dut/hart/StallF
add wave /testbench/dut/hart/StallD add wave /testbench/dut/hart/StallD
add wave /testbench/dut/hart/StallE add wave /testbench/dut/hart/StallE

2
wally-pipelined/regression/wave-dos/cache-waves.do
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@ -4,7 +4,7 @@ add wave -divider
#add wave /testbench/dut/hart/ebu/IReadF #add wave /testbench/dut/hart/ebu/IReadF
add wave /testbench/dut/hart/DataStall add wave /testbench/dut/hart/DataStall
add wave /testbench/dut/hart/InstrStall add wave /testbench/dut/hart/ICacheStallF
add wave /testbench/dut/hart/StallF add wave /testbench/dut/hart/StallF
add wave /testbench/dut/hart/StallD add wave /testbench/dut/hart/StallD
add wave /testbench/dut/hart/StallE add wave /testbench/dut/hart/StallE

2
wally-pipelined/regression/wave-dos/default-waves.do
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@ -6,7 +6,7 @@ add wave /testbench/reset
add wave -divider add wave -divider
#add wave /testbench/dut/hart/ebu/IReadF #add wave /testbench/dut/hart/ebu/IReadF
add wave /testbench/dut/hart/DataStall add wave /testbench/dut/hart/DataStall
add wave /testbench/dut/hart/InstrStall add wave /testbench/dut/hart/ICacheStallF
add wave /testbench/dut/hart/StallF add wave /testbench/dut/hart/StallF
add wave /testbench/dut/hart/StallD add wave /testbench/dut/hart/StallD
add wave /testbench/dut/hart/StallE add wave /testbench/dut/hart/StallE

6
wally-pipelined/src/ifu/icache.sv
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@ -126,7 +126,7 @@ module icachecontroller #(parameter LINESIZE = 256) (
); );
logic [31:0] AlignedInstrRawF, AlignedInstrRawD; logic [31:0] AlignedInstrRawF, AlignedInstrRawD;
logic FlushDLastCycle; logic FlushDLastCycleN;
const logic [31:0] NOP = 32'h13; const logic [31:0] NOP = 32'h13;
// TODO allow compressed instructions // TODO allow compressed instructions
@ -148,8 +148,8 @@ module icachecontroller #(parameter LINESIZE = 256) (
endgenerate endgenerate
flopenr #(32) AlignedInstrRawDFlop(clk, reset, ~StallD, AlignedInstrRawF, AlignedInstrRawD); flopenr #(32) AlignedInstrRawDFlop(clk, reset, ~StallD, AlignedInstrRawF, AlignedInstrRawD);
flopr #(1) FlushDLastCycleFlop(clk, reset, FlushD | (FlushDLastCycle & StallF), FlushDLastCycle); flopr #(1) FlushDLastCycleFlop(clk, reset, ~FlushD & (FlushDLastCycleN | ~StallF), FlushDLastCycleN);
mux2 #(32) InstrRawDMux(AlignedInstrRawD, NOP, FlushDLastCycle, InstrRawD); mux2 #(32) InstrRawDMux(AlignedInstrRawD, NOP, ~FlushDLastCycleN, InstrRawD);
// Handle cache faults // Handle cache faults