diff --git a/wally-pipelined/regression/wave-dos/ahb-waves.do b/wally-pipelined/regression/wave-dos/ahb-waves.do index c3a38563d..c542f5841 100644 --- a/wally-pipelined/regression/wave-dos/ahb-waves.do +++ b/wally-pipelined/regression/wave-dos/ahb-waves.do @@ -4,7 +4,7 @@ add wave -divider #add wave /testbench/dut/hart/ebu/IReadF add wave /testbench/dut/hart/DataStall -add wave /testbench/dut/hart/InstrStall +add wave /testbench/dut/hart/ICacheStallF add wave /testbench/dut/hart/StallF add wave /testbench/dut/hart/StallD add wave /testbench/dut/hart/StallE diff --git a/wally-pipelined/regression/wave-dos/cache-waves.do b/wally-pipelined/regression/wave-dos/cache-waves.do index e39d40a07..bdd88a13f 100644 --- a/wally-pipelined/regression/wave-dos/cache-waves.do +++ b/wally-pipelined/regression/wave-dos/cache-waves.do @@ -4,7 +4,7 @@ add wave -divider #add wave /testbench/dut/hart/ebu/IReadF add wave /testbench/dut/hart/DataStall -add wave /testbench/dut/hart/InstrStall +add wave /testbench/dut/hart/ICacheStallF add wave /testbench/dut/hart/StallF add wave /testbench/dut/hart/StallD add wave /testbench/dut/hart/StallE diff --git a/wally-pipelined/regression/wave-dos/default-waves.do b/wally-pipelined/regression/wave-dos/default-waves.do index ef4e30c61..3f81cfad6 100644 --- a/wally-pipelined/regression/wave-dos/default-waves.do +++ b/wally-pipelined/regression/wave-dos/default-waves.do @@ -6,7 +6,7 @@ add wave /testbench/reset add wave -divider #add wave /testbench/dut/hart/ebu/IReadF add wave /testbench/dut/hart/DataStall -add wave /testbench/dut/hart/InstrStall +add wave /testbench/dut/hart/ICacheStallF add wave /testbench/dut/hart/StallF add wave /testbench/dut/hart/StallD add wave /testbench/dut/hart/StallE diff --git a/wally-pipelined/src/ifu/icache.sv b/wally-pipelined/src/ifu/icache.sv index df608a39f..631a9bd6d 100644 --- a/wally-pipelined/src/ifu/icache.sv +++ b/wally-pipelined/src/ifu/icache.sv @@ -126,7 +126,7 @@ module icachecontroller #(parameter LINESIZE = 256) ( ); logic [31:0] AlignedInstrRawF, AlignedInstrRawD; - logic FlushDLastCycle; + logic FlushDLastCycleN; const logic [31:0] NOP = 32'h13; // TODO allow compressed instructions @@ -148,8 +148,8 @@ module icachecontroller #(parameter LINESIZE = 256) ( endgenerate flopenr #(32) AlignedInstrRawDFlop(clk, reset, ~StallD, AlignedInstrRawF, AlignedInstrRawD); - flopr #(1) FlushDLastCycleFlop(clk, reset, FlushD | (FlushDLastCycle & StallF), FlushDLastCycle); - mux2 #(32) InstrRawDMux(AlignedInstrRawD, NOP, FlushDLastCycle, InstrRawD); + flopr #(1) FlushDLastCycleFlop(clk, reset, ~FlushD & (FlushDLastCycleN | ~StallF), FlushDLastCycleN); + mux2 #(32) InstrRawDMux(AlignedInstrRawD, NOP, ~FlushDLastCycleN, InstrRawD); // Handle cache faults