Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'main' of github.com:openhwgroup/cvw into boot

Browse Source
This commit is contained in:
Jacob Pease 2023-01-26 23:09:01 -06:00
commit fc36725ddd
7 changed files with 104 additions and 112 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitignore vendored
View File

@ -76,7 +76,7 @@ synthDC/runs/
synthDC/newRuns synthDC/newRuns
synthDC/ppa/PPAruns synthDC/ppa/PPAruns
synthDC/ppa/plots synthDC/ppa/plots
synthDC/plots/ synthDC/wallyplots/
synthDC/runArchive synthDC/runArchive
synthDC/hdl synthDC/hdl
/pipelined/regression/power.saif /pipelined/regression/power.saif

1
addins/imperas-riscv-tests
View File

@ -1 +0,0 @@
/opt/riscv/imperas-riscv-tests/

2
examples/C/sum/Makefile
View File

@ -4,7 +4,7 @@ $(TARGET).objdump: $(TARGET)
riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
$(TARGET): $(TARGET).c Makefile $(TARGET): $(TARGET).c Makefile
riscv64-unknown-elf-gcc -o $(TARGET) -g -O\ riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\
-march=rv64gc -mabi=lp64d -mcmodel=medany \ -march=rv64gc -mabi=lp64d -mcmodel=medany \
-nostdlib -static -lm -fno-tree-loop-distribute-patterns \ -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-T../common/test.ld -I../common \ -T../common/test.ld -I../common \

54
pipelined/src/ifu/brpred/bpred.sv
View File

@ -29,36 +29,36 @@
`include "wally-config.vh" `include "wally-config.vh"
module bpred ( module bpred (
input logic clk, reset, input logic clk, reset,
input logic StallF, StallD, StallE, StallM, StallW, input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW, input logic FlushD, FlushE, FlushM, FlushW,
// Fetch stage // Fetch stage
// the prediction // the prediction
input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class
input logic [`XLEN-1:0] PCNextF, // Next Fetch Address input logic [`XLEN-1:0] PCNextF, // Next Fetch Address
input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4 input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4
output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction
output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage
// Update Predictor // Update Predictor
input logic [`XLEN-1:0] PCF, // Fetch stage instruction address input logic [`XLEN-1:0] PCF, // Fetch stage instruction address
input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took
input logic [`XLEN-1:0] PCE, // Execution stage instruction address input logic [`XLEN-1:0] PCE, // Execution stage instruction address
input logic [`XLEN-1:0] PCM, // Memory stage instruction address input logic [`XLEN-1:0] PCM, // Memory stage instruction address
// Branch and jump outcome // Branch and jump outcome
input logic PCSrcE, // Executation stage branch is taken input logic PCSrcE, // Executation stage branch is taken
input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) input logic [`XLEN-1:0] dPCLinkE, // The address following the branch instruction. (AKA Fall through address)
output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
// Report branch prediction status // Report branch prediction status
output logic BPPredWrongE, // Prediction is wrong output logic BPPredWrongE, // Prediction is wrong
output logic DirPredictionWrongM, // Prediction direction is wrong output logic DirPredictionWrongM, // Prediction direction is wrong
output logic BTBPredPCWrongM, // Prediction target wrong output logic BTBPredPCWrongM, // Prediction target wrong
output logic RASPredPCWrongM, // RAS prediction is wrong output logic RASPredPCWrongM, // RAS prediction is wrong
output logic PredictionInstrClassWrongM // Class prediction is wrong output logic PredictionInstrClassWrongM // Class prediction is wrong
); );
logic BTBValidF; logic BTBValidF;
logic [1:0] DirPredictionF; logic [1:0] DirPredictionF;

72
synthDC/Makefile
View File

@ -8,6 +8,7 @@ NAME := synth
export DESIGN ?= wallypipelinedcore export DESIGN ?= wallypipelinedcore
export FREQ ?= 3000 export FREQ ?= 3000
export CONFIG ?= rv32e export CONFIG ?= rv32e
export MOD ?= orig
# title to add a note in the synth's directory name # title to add a note in the synth's directory name
TITLE = TITLE =
# tsmc28, sky130, and sky90 presently supported # tsmc28, sky130, and sky90 presently supported
@ -22,13 +23,15 @@ export DRIVE ?= FLOP
time := $(shell date +%F-%H-%M) time := $(shell date +%F-%H-%M)
hash := $(shell git rev-parse --short HEAD) hash := $(shell git rev-parse --short HEAD)
export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
export SAIFPOWER ?= 0 export SAIFPOWER ?= 0
CONFIGDIR ?= ${WALLY}/pipelined/config configAsList := $(subst _, ,$(CONFIG))
BASECONFIG := $(word 1, $(configAsList))
OLDCONFIGDIR ?= ${WALLY}/pipelined/config
CONFIGDIR ?= $(OUTPUTDIR)/hdl/config
CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*)
CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) CONFIGFILESTRIM = $(notdir $(CONFIGFILES))
# FREQS = 25 50 100 150 200 250 300 350 400
# k = 3 6 # k = 3 6
print: print:
@ -42,8 +45,8 @@ default:
@echo "Use wallySynth.py to run a concurrent sweep " @echo "Use wallySynth.py to run a concurrent sweep "
DIRS32 = rv32e rv32gc rv32ic DIRS32 = rv32e rv32gc rv32ic rv32i
DIRS64 = rv64ic rv64gc DIRS64 = rv64i rv64gc
DIRS = $(DIRS32) $(DIRS64) DIRS = $(DIRS32) $(DIRS64)
# bpred: # bpred:
@ -51,73 +54,72 @@ DIRS = $(DIRS32) $(DIRS64)
# @$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);) # @$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);)
# @$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;) # @$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;)
# @$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;) # @$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;)
copy:
# remove old config files
rm -rf $(CONFIGDIR)/*_*
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) configs: $(BASECONFIG)
@$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;) $(BASECONFIG):
@$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) @echo $(BASECONFIG)
@$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) cp -r $(OLDCONFIGDIR)/$(BASECONFIG) $(CONFIGDIR)/$(BASECONFIG)_orig
@$(foreach dir, $(DIRS), sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
@$(foreach dir, $(DIRS32), sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;) ifneq ($(filter $ $(BASECONFIG), $(DIRS32)),)
@$(foreach dir, $(DIRS64), sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;) sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
else ifneq ($(filter $ $(BASECONFIG), $(DIRS64)),)
configs: $(DIRS) sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh
$(DIRS): else
$(info $(BASECONFIG) does not exist in $(DIRS32) or $(DIRS64))
@echo "Config not in list, RAM_RANGE will be unmodified"
endif
# turn off FPU # turn off FPU
rm -rf $(CONFIGDIR)/$@_FPUoff
cp -r $(CONFIGDIR)/$@_orig $(CONFIGDIR)/$@_FPUoff cp -r $(CONFIGDIR)/$@_orig $(CONFIGDIR)/$@_FPUoff
sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh
sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh
# PMP 16 # PMP 16
rm -rf $(CONFIGDIR)/$@_PMP16
cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16 cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16
sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh
# PMP 0 # PMP 0
rm -rf $(CONFIGDIR)/$@_PMP0
cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0 cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0
sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh
# no muldiv # no muldiv
rm -rf $(CONFIGDIR)/$@_noMulDiv
cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv
sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh
# no priv # no priv
rm -rf $(CONFIGDIR)/$@_noPriv
cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv
sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
ifeq ($(SAIFPOWER), 1)
cp -f ../pipelined/regression/power.saif .
endif
freqs: freqs:
@$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;) @$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;)
synth: mkdirecs:
@echo "DC Synthesis" @echo "DC Synthesis"
@mkdir -p $(OUTPUTDIR) @mkdir -p $(OUTPUTDIR)
@mkdir -p $(OUTPUTDIR)/hdl @mkdir -p $(OUTPUTDIR)/hdl/config
@mkdir -p $(OUTPUTDIR)/reports @mkdir -p $(OUTPUTDIR)/reports
@mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/mapped
@mkdir -p $(OUTPUTDIR)/unmapped @mkdir -p $(OUTPUTDIR)/unmapped
ifeq ($(SAIFPOWER), 1)
cp -f ../pipelined/regression/power.saif . synth: mkdirecs configs rundc clean
endif
rundc:
dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
# rm -rf $(OUTPUTDIR)/hdl
clean:
rm -rf $(OUTPUTDIR)/hdl
rm -rf $(OUTPUTDIR)/WORK rm -rf $(OUTPUTDIR)/WORK
rm -rf $(OUTPUTDIR)/alib-52 rm -rf $(OUTPUTDIR)/alib-52
clean:
rm -f default.svf rm -f default.svf
rm -f command.log rm -f command.log
rm -f filenames*.log rm -f filenames*.log
rm -f power.saif rm -f power.saif
rm -f Synopsys_stack_trace_*.txt rm -f Synopsys_stack_trace_*.txt
rm -f crte_*.txt rm -f crte_*.txt
fresh: clean copy configs
@echo "synth directory cleaned and fresh config files written"

54
synthDC/extractSummary.py
View File

@ -28,16 +28,16 @@ def synthsintocsv():
file = open("Summary.csv", "w") file = open("Summary.csv", "w")
writer = csv.writer(file) writer = csv.writer(file)
writer.writerow(['Width', 'Config', 'Special', 'Tech', 'Target Freq', 'Delay', 'Area']) writer.writerow(['Width', 'Config', 'Mod', 'Tech', 'Target Freq', 'Delay', 'Area'])
for oneSynth in allSynths: for oneSynth in allSynths:
descrip = specReg.findall(oneSynth) descrip = specReg.findall(oneSynth)
width = descrip[2][:4] width = descrip[2][:4]
config = descrip[2][4:] config = descrip[2][4:]
if descrip[3][-2:] == 'nm': if descrip[3][-2:] == 'nm':
special = '' mod = ''
else: else:
special = descrip[3] mod = descrip[3]
descrip = descrip[1:] descrip = descrip[1:]
tech = descrip[3][:-2] tech = descrip[3][:-2]
freq = descrip[4] freq = descrip[4]
@ -57,12 +57,12 @@ def synthsintocsv():
else: else:
delay = 1000/int(freq) - metrics[0] delay = 1000/int(freq) - metrics[0]
area = metrics[1] area = metrics[1]
writer.writerow([width, config, special, tech, freq, delay, area]) writer.writerow([width, config, mod, tech, freq, delay, area])
file.close() file.close()
def synthsfromcsv(filename): def synthsfromcsv(filename):
Synth = namedtuple("Synth", "width config special tech freq delay area") Synth = namedtuple("Synth", "width config mod tech freq delay area")
with open(filename, newline='') as csvfile: with open(filename, newline='') as csvfile:
csvreader = csv.reader(csvfile) csvreader = csv.reader(csvfile)
global allSynths global allSynths
@ -81,14 +81,9 @@ def freqPlot(tech, width, config):
''' plots delay, area for syntheses with specified tech, module, width ''' plots delay, area for syntheses with specified tech, module, width
''' '''
current_directory = os.getcwd()
final_directory = os.path.join(current_directory, 'plots/wally')
if not os.path.exists(final_directory):
os.makedirs(final_directory)
freqsL, delaysL, areasL = ([[], []] for i in range(3)) freqsL, delaysL, areasL = ([[], []] for i in range(3))
for oneSynth in allSynths: for oneSynth in allSynths:
if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('' == oneSynth.special): if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('orig' == oneSynth.mod):
ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period
freqsL[ind] += [oneSynth.freq] freqsL[ind] += [oneSynth.freq]
delaysL[ind] += [oneSynth.delay] delaysL[ind] += [oneSynth.delay]
@ -130,7 +125,7 @@ def freqPlot(tech, width, config):
ax2.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}')) ax2.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}'))
addFO4axis(fig, ax1, tech) addFO4axis(fig, ax1, tech)
plt.savefig('./plots/wally/freqSweep_' + tech + '_' + width + config + '.png') plt.savefig(final_directory + '/freqSweep_' + tech + '_' + width + config + '.png')
def areaDelay(tech, delays, areas, labels, fig, ax, norm=False): def areaDelay(tech, delays, areas, labels, fig, ax, norm=False):
@ -168,7 +163,7 @@ def plotFeatures(tech, width, config):
if (oneSynth.config == config) & (width == oneSynth.width): if (oneSynth.config == config) & (width == oneSynth.width):
delays += [oneSynth.delay] delays += [oneSynth.delay]
areas += [oneSynth.area] areas += [oneSynth.area]
labels += [oneSynth.special] labels += [oneSynth.mod]
fig, (ax) = plt.subplots(1, 1) fig, (ax) = plt.subplots(1, 1)
@ -176,28 +171,28 @@ def plotFeatures(tech, width, config):
titlestr = tech+'_'+width+config titlestr = tech+'_'+width+config
plt.title(titlestr) plt.title(titlestr)
plt.savefig('./plots/wally/features_'+titlestr+'.png') plt.savefig(final_directory + '/features_'+titlestr+'.png')
def plotConfigs(tech, special=''): def plotConfigs(tech, mod=''):
delays, areas, labels = ([] for i in range(3)) delays, areas, labels = ([] for i in range(3))
freq = techdict[tech].targfreq freq = techdict[tech].targfreq
for oneSynth in allSynths: for oneSynth in allSynths:
if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special): if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.mod == mod):
delays += [oneSynth.delay] delays += [oneSynth.delay]
areas += [oneSynth.area] areas += [oneSynth.area]
labels += [oneSynth.width + oneSynth.config] labels += [oneSynth.width + oneSynth.config]
fig, (ax) = plt.subplots(1, 1) fig, (ax) = plt.subplots(1, 1)
fig = areaDelay(tech, delays, areas, labels, fig, ax) fig = areaDelay(tech, delays, areas, labels, fig, ax)
titleStr = tech+'_'+special titleStr = tech+'_'+mod
plt.title(titleStr) plt.title(titleStr)
plt.savefig('./plots/wally/configs_' + titleStr + '.png') plt.savefig(final_directory + '/configs_' + titleStr + '.png')
def normAreaDelay(special=''): def normAreaDelay(mod=''):
fig, (ax) = plt.subplots(1, 1) fig, (ax) = plt.subplots(1, 1)
fullLeg = [] fullLeg = []
for tech in list(techdict.keys()): for tech in list(techdict.keys()):
@ -205,7 +200,7 @@ def normAreaDelay(special=''):
spec = techdict[tech] spec = techdict[tech]
freq = spec.targfreq freq = spec.targfreq
for oneSynth in allSynths: for oneSynth in allSynths:
if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special): if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.mod == mod):
delays += [oneSynth.delay] delays += [oneSynth.delay]
areas += [oneSynth.area] areas += [oneSynth.area]
labels += [oneSynth.width + oneSynth.config] labels += [oneSynth.width + oneSynth.config]
@ -216,7 +211,7 @@ def normAreaDelay(special=''):
ax.set_xlabel('Cycle Time (FO4)') ax.set_xlabel('Cycle Time (FO4)')
ax.set_ylabel('Area (add32)') ax.set_ylabel('Area (add32)')
ax.legend(handles = fullLeg, loc='upper left') ax.legend(handles = fullLeg, loc='upper left')
plt.savefig('./plots/wally/normAreaDelay.png') plt.savefig(final_directory + '/normAreaDelay.png')
def addFO4axis(fig, ax, tech): def addFO4axis(fig, ax, tech):
@ -254,12 +249,17 @@ if __name__ == '__main__':
techdict['sky90'] = TechSpec('green', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023) techdict['sky90'] = TechSpec('green', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023)
techdict['tsmc28'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533) techdict['tsmc28'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533)
current_directory = os.getcwd()
final_directory = os.path.join(current_directory, 'wallyplots')
if not os.path.exists(final_directory):
os.makedirs(final_directory)
synthsintocsv() synthsintocsv()
synthsfromcsv('Summary.csv') synthsfromcsv('Summary.csv')
freqPlot('tsmc28', 'rv32', 'e') freqPlot('tsmc28', 'rv32', 'e')
freqPlot('sky90', 'rv32', 'e') freqPlot('sky90', 'rv32', 'e')
plotFeatures('sky90', 'rv64', 'gc') plotFeatures('sky90', 'rv64', 'gc')
plotFeatures('tsmc28', 'rv64', 'gc') plotFeatures('tsmc28', 'rv64', 'gc')
plotConfigs('sky90', special='orig') plotConfigs('sky90', mod='orig')
plotConfigs('tsmc28', special='orig') plotConfigs('tsmc28', mod='orig')
normAreaDelay(special='orig') normAreaDelay(mod='orig')

31
synthDC/wallySynth.py
View File

@ -5,20 +5,14 @@ import subprocess
from multiprocessing import Pool from multiprocessing import Pool
import argparse import argparse
def runSynth(config, tech, freq, maxopt): def runSynth(config, mod, tech, freq, maxopt):
global pool global pool
command = "make synth DESIGN=wallypipelinedcore CONFIG={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, tech, freq, maxopt) command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, mod, tech, freq, maxopt)
pool.map(mask, [command]) pool.map(mask, [command])
def mask(command): def mask(command):
subprocess.Popen(command, shell=True) subprocess.Popen(command, shell=True)
def freshStart():
out = subprocess.check_output(['bash','-c', 'make fresh'])
for x in out.decode("utf-8").split('\n')[:-1]:
print(x)
return
if __name__ == '__main__': if __name__ == '__main__':
@ -41,24 +35,21 @@ if __name__ == '__main__':
args = parser.parse_args() args = parser.parse_args()
freq = args.targetfreq if args.targetfreq else 3000
tech = args.tech if args.tech else 'sky90' tech = args.tech if args.tech else 'sky90'
defaultfreq = 3000 if tech == 'sky90' else 10000
freq = args.targetfreq if args.targetfreq else defaultfreq
maxopt = int(args.maxopt) maxopt = int(args.maxopt)
mod = 'orig' # until memory integrated
if args.freqsweep: if args.freqsweep:
sc = args.freqsweep sc = args.freqsweep
config = args.version if args.version else 'rv32e' config = args.version if args.version else 'rv32e'
freshStart()
for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep
runSynth(config, tech, freq, maxopt) runSynth(config, mod, tech, freq, maxopt)
if args.configsweep: if args.configsweep:
freshStart() for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32ic', 'rv32e']: #configs
for config in ['rv32gc', 'rv32ic', 'rv64gc', 'rv64ic', 'rv32e']: # configs runSynth(config, mod, tech, freq, maxopt)
config = config + '_orig' # until memory integrated
runSynth(config, tech, freq, maxopt)
if args.featuresweep: if args.featuresweep:
freshStart() config = args.version if args.version else 'rv64gc'
v = args.version if args.version else 'rv64gc' for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations 'orig',
for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations runSynth(config, mod, tech, freq, maxopt)
config = v + '_' + mod
runSynth(config, tech, freq, maxopt)