From 30b085911ae5b027fe563405b337891a2411982b Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 24 Jan 2023 05:42:34 -0800 Subject: [PATCH 1/5] bpred tab cleanup --- pipelined/src/ifu/bpred.sv | 54 +++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index ab47d678f..94d0d692f 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -29,36 +29,36 @@ `include "wally-config.vh" module bpred ( - input logic clk, reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - // Fetch stage - // the prediction - input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class - input logic [`XLEN-1:0] PCNextF, // Next Fetch Address - input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4 - output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction - output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage + input logic clk, reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, + // Fetch stage + // the prediction + input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class + input logic [`XLEN-1:0] PCNextF, // Next Fetch Address + input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4 + output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction + output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage - // Update Predictor - input logic [`XLEN-1:0] PCF, // Fetch stage instruction address - input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took - input logic [`XLEN-1:0] PCE, // Execution stage instruction address - input logic [`XLEN-1:0] PCM, // Memory stage instruction address + // Update Predictor + input logic [`XLEN-1:0] PCF, // Fetch stage instruction address + input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took + input logic [`XLEN-1:0] PCE, // Execution stage instruction address + input logic [`XLEN-1:0] PCM, // Memory stage instruction address - // Branch and jump outcome - input logic PCSrcE, // Executation stage branch is taken - input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address - input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) - output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br + // Branch and jump outcome + input logic PCSrcE, // Executation stage branch is taken + input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address + input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) + output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br - // Report branch prediction status - output logic BPPredWrongE, // Prediction is wrong - output logic DirPredictionWrongM, // Prediction direction is wrong - output logic BTBPredPCWrongM, // Prediction target wrong - output logic RASPredPCWrongM, // RAS prediction is wrong - output logic PredictionInstrClassWrongM // Class prediction is wrong - ); + // Report branch prediction status + output logic BPPredWrongE, // Prediction is wrong + output logic DirPredictionWrongM, // Prediction direction is wrong + output logic BTBPredPCWrongM, // Prediction target wrong + output logic RASPredPCWrongM, // RAS prediction is wrong + output logic PredictionInstrClassWrongM // Class prediction is wrong +); logic BTBValidF; logic [1:0] DirPredictionF; From 0e5ea5f51d4e7bee18dab0e3fb2402cff4e775f4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 24 Jan 2023 06:14:31 -0800 Subject: [PATCH 2/5] bpred input spacing cleanup --- pipelined/src/ifu/bpred.sv | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index 94d0d692f..d321169f4 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -29,27 +29,27 @@ `include "wally-config.vh" module bpred ( - input logic clk, reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, + input logic clk, reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, // Fetch stage // the prediction - input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class - input logic [`XLEN-1:0] PCNextF, // Next Fetch Address - input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4 + input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class + input logic [`XLEN-1:0] PCNextF, // Next Fetch Address + input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4 output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage // Update Predictor - input logic [`XLEN-1:0] PCF, // Fetch stage instruction address - input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took - input logic [`XLEN-1:0] PCE, // Execution stage instruction address - input logic [`XLEN-1:0] PCM, // Memory stage instruction address + input logic [`XLEN-1:0] PCF, // Fetch stage instruction address + input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took + input logic [`XLEN-1:0] PCE, // Execution stage instruction address + input logic [`XLEN-1:0] PCM, // Memory stage instruction address // Branch and jump outcome - input logic PCSrcE, // Executation stage branch is taken - input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address - input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) + input logic PCSrcE, // Executation stage branch is taken + input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address + input logic [`XLEN-1:0] dPCLinkE, // The address following the branch instruction. (AKA Fall through address) output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br // Report branch prediction status From 6ece31183c4c6bedb2bda7e8e6ef02aafd2df92c Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Thu, 26 Jan 2023 06:58:15 +0200 Subject: [PATCH 3/5] Fixed config file writing for synthesis (#29) * Fixed writing config files for synth sweeps * cleaned up comments --- .gitignore | 2 +- synthDC/Makefile | 72 ++++++++++++++++++++------------------- synthDC/extractSummary.py | 54 ++++++++++++++--------------- synthDC/wallySynth.py | 31 ++++++----------- 4 files changed, 76 insertions(+), 83 deletions(-) diff --git a/.gitignore b/.gitignore index c4c71a623..609ef1487 100644 --- a/.gitignore +++ b/.gitignore @@ -76,7 +76,7 @@ synthDC/runs/ synthDC/newRuns synthDC/ppa/PPAruns synthDC/ppa/plots -synthDC/plots/ +synthDC/wallyplots/ synthDC/runArchive synthDC/hdl /pipelined/regression/power.saif diff --git a/synthDC/Makefile b/synthDC/Makefile index 98b719428..81d982251 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -8,6 +8,7 @@ NAME := synth export DESIGN ?= wallypipelinedcore export FREQ ?= 3000 export CONFIG ?= rv32e +export MOD ?= orig # title to add a note in the synth's directory name TITLE = # tsmc28, sky130, and sky90 presently supported @@ -22,13 +23,15 @@ export DRIVE ?= FLOP time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) -export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) +export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) export SAIFPOWER ?= 0 -CONFIGDIR ?= ${WALLY}/pipelined/config +configAsList := $(subst _, ,$(CONFIG)) +BASECONFIG := $(word 1, $(configAsList)) +OLDCONFIGDIR ?= ${WALLY}/pipelined/config +CONFIGDIR ?= $(OUTPUTDIR)/hdl/config CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) -# FREQS = 25 50 100 150 200 250 300 350 400 # k = 3 6 print: @@ -42,8 +45,8 @@ default: @echo "Use wallySynth.py to run a concurrent sweep " -DIRS32 = rv32e rv32gc rv32ic -DIRS64 = rv64ic rv64gc +DIRS32 = rv32e rv32gc rv32ic rv32i +DIRS64 = rv64i rv64gc DIRS = $(DIRS32) $(DIRS64) # bpred: @@ -51,73 +54,72 @@ DIRS = $(DIRS32) $(DIRS64) # @$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);) # @$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;) # @$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;) -copy: - # remove old config files - rm -rf $(CONFIGDIR)/*_* - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) - @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;) - @$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) - @$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) - @$(foreach dir, $(DIRS), sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) +configs: $(BASECONFIG) +$(BASECONFIG): + @echo $(BASECONFIG) + cp -r $(OLDCONFIGDIR)/$(BASECONFIG) $(CONFIGDIR)/$(BASECONFIG)_orig + sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh + sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh + sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh - @$(foreach dir, $(DIRS32), sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;) - @$(foreach dir, $(DIRS64), sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;) - -configs: $(DIRS) -$(DIRS): +ifneq ($(filter $ $(BASECONFIG), $(DIRS32)),) + sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh +else ifneq ($(filter $ $(BASECONFIG), $(DIRS64)),) + sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh +else + $(info $(BASECONFIG) does not exist in $(DIRS32) or $(DIRS64)) + @echo "Config not in list, RAM_RANGE will be unmodified" +endif # turn off FPU - rm -rf $(CONFIGDIR)/$@_FPUoff cp -r $(CONFIGDIR)/$@_orig $(CONFIGDIR)/$@_FPUoff sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh # PMP 16 - rm -rf $(CONFIGDIR)/$@_PMP16 cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16 sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh # PMP 0 - rm -rf $(CONFIGDIR)/$@_PMP0 cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0 sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh # no muldiv - rm -rf $(CONFIGDIR)/$@_noMulDiv cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh # no priv - rm -rf $(CONFIGDIR)/$@_noPriv cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh +ifeq ($(SAIFPOWER), 1) + cp -f ../pipelined/regression/power.saif . +endif + freqs: @$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;) -synth: +mkdirecs: @echo "DC Synthesis" @mkdir -p $(OUTPUTDIR) - @mkdir -p $(OUTPUTDIR)/hdl + @mkdir -p $(OUTPUTDIR)/hdl/config @mkdir -p $(OUTPUTDIR)/reports @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped -ifeq ($(SAIFPOWER), 1) - cp -f ../pipelined/regression/power.saif . -endif + +synth: mkdirecs configs rundc clean + +rundc: dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out -# rm -rf $(OUTPUTDIR)/hdl + +clean: + rm -rf $(OUTPUTDIR)/hdl rm -rf $(OUTPUTDIR)/WORK rm -rf $(OUTPUTDIR)/alib-52 - -clean: rm -f default.svf rm -f command.log rm -f filenames*.log rm -f power.saif rm -f Synopsys_stack_trace_*.txt - rm -f crte_*.txt - -fresh: clean copy configs - @echo "synth directory cleaned and fresh config files written" + rm -f crte_*.txt \ No newline at end of file diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 978365b16..430f86178 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -28,16 +28,16 @@ def synthsintocsv(): file = open("Summary.csv", "w") writer = csv.writer(file) - writer.writerow(['Width', 'Config', 'Special', 'Tech', 'Target Freq', 'Delay', 'Area']) + writer.writerow(['Width', 'Config', 'Mod', 'Tech', 'Target Freq', 'Delay', 'Area']) for oneSynth in allSynths: descrip = specReg.findall(oneSynth) width = descrip[2][:4] config = descrip[2][4:] if descrip[3][-2:] == 'nm': - special = '' + mod = '' else: - special = descrip[3] + mod = descrip[3] descrip = descrip[1:] tech = descrip[3][:-2] freq = descrip[4] @@ -57,12 +57,12 @@ def synthsintocsv(): else: delay = 1000/int(freq) - metrics[0] area = metrics[1] - writer.writerow([width, config, special, tech, freq, delay, area]) + writer.writerow([width, config, mod, tech, freq, delay, area]) file.close() def synthsfromcsv(filename): - Synth = namedtuple("Synth", "width config special tech freq delay area") + Synth = namedtuple("Synth", "width config mod tech freq delay area") with open(filename, newline='') as csvfile: csvreader = csv.reader(csvfile) global allSynths @@ -81,14 +81,9 @@ def freqPlot(tech, width, config): ''' plots delay, area for syntheses with specified tech, module, width ''' - current_directory = os.getcwd() - final_directory = os.path.join(current_directory, 'plots/wally') - if not os.path.exists(final_directory): - os.makedirs(final_directory) - freqsL, delaysL, areasL = ([[], []] for i in range(3)) for oneSynth in allSynths: - if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('' == oneSynth.special): + if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('orig' == oneSynth.mod): ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period freqsL[ind] += [oneSynth.freq] delaysL[ind] += [oneSynth.delay] @@ -130,7 +125,7 @@ def freqPlot(tech, width, config): ax2.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}')) addFO4axis(fig, ax1, tech) - plt.savefig('./plots/wally/freqSweep_' + tech + '_' + width + config + '.png') + plt.savefig(final_directory + '/freqSweep_' + tech + '_' + width + config + '.png') def areaDelay(tech, delays, areas, labels, fig, ax, norm=False): @@ -168,7 +163,7 @@ def plotFeatures(tech, width, config): if (oneSynth.config == config) & (width == oneSynth.width): delays += [oneSynth.delay] areas += [oneSynth.area] - labels += [oneSynth.special] + labels += [oneSynth.mod] fig, (ax) = plt.subplots(1, 1) @@ -176,28 +171,28 @@ def plotFeatures(tech, width, config): titlestr = tech+'_'+width+config plt.title(titlestr) - plt.savefig('./plots/wally/features_'+titlestr+'.png') + plt.savefig(final_directory + '/features_'+titlestr+'.png') -def plotConfigs(tech, special=''): +def plotConfigs(tech, mod=''): delays, areas, labels = ([] for i in range(3)) freq = techdict[tech].targfreq for oneSynth in allSynths: - if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special): - delays += [oneSynth.delay] - areas += [oneSynth.area] - labels += [oneSynth.width + oneSynth.config] + if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.mod == mod): + delays += [oneSynth.delay] + areas += [oneSynth.area] + labels += [oneSynth.width + oneSynth.config] fig, (ax) = plt.subplots(1, 1) fig = areaDelay(tech, delays, areas, labels, fig, ax) - titleStr = tech+'_'+special + titleStr = tech+'_'+mod plt.title(titleStr) - plt.savefig('./plots/wally/configs_' + titleStr + '.png') + plt.savefig(final_directory + '/configs_' + titleStr + '.png') -def normAreaDelay(special=''): +def normAreaDelay(mod=''): fig, (ax) = plt.subplots(1, 1) fullLeg = [] for tech in list(techdict.keys()): @@ -205,7 +200,7 @@ def normAreaDelay(special=''): spec = techdict[tech] freq = spec.targfreq for oneSynth in allSynths: - if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special): + if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.mod == mod): delays += [oneSynth.delay] areas += [oneSynth.area] labels += [oneSynth.width + oneSynth.config] @@ -216,7 +211,7 @@ def normAreaDelay(special=''): ax.set_xlabel('Cycle Time (FO4)') ax.set_ylabel('Area (add32)') ax.legend(handles = fullLeg, loc='upper left') - plt.savefig('./plots/wally/normAreaDelay.png') + plt.savefig(final_directory + '/normAreaDelay.png') def addFO4axis(fig, ax, tech): @@ -254,12 +249,17 @@ if __name__ == '__main__': techdict['sky90'] = TechSpec('green', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023) techdict['tsmc28'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533) + current_directory = os.getcwd() + final_directory = os.path.join(current_directory, 'wallyplots') + if not os.path.exists(final_directory): + os.makedirs(final_directory) + synthsintocsv() synthsfromcsv('Summary.csv') freqPlot('tsmc28', 'rv32', 'e') freqPlot('sky90', 'rv32', 'e') plotFeatures('sky90', 'rv64', 'gc') plotFeatures('tsmc28', 'rv64', 'gc') - plotConfigs('sky90', special='orig') - plotConfigs('tsmc28', special='orig') - normAreaDelay(special='orig') + plotConfigs('sky90', mod='orig') + plotConfigs('tsmc28', mod='orig') + normAreaDelay(mod='orig') diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 0c1579813..6b10f2e8b 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -5,20 +5,14 @@ import subprocess from multiprocessing import Pool import argparse -def runSynth(config, tech, freq, maxopt): +def runSynth(config, mod, tech, freq, maxopt): global pool - command = "make synth DESIGN=wallypipelinedcore CONFIG={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, tech, freq, maxopt) + command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, mod, tech, freq, maxopt) pool.map(mask, [command]) def mask(command): subprocess.Popen(command, shell=True) -def freshStart(): - out = subprocess.check_output(['bash','-c', 'make fresh']) - for x in out.decode("utf-8").split('\n')[:-1]: - print(x) - return - if __name__ == '__main__': @@ -41,24 +35,21 @@ if __name__ == '__main__': args = parser.parse_args() - freq = args.targetfreq if args.targetfreq else 3000 tech = args.tech if args.tech else 'sky90' + defaultfreq = 3000 if tech == 'sky90' else 10000 + freq = args.targetfreq if args.targetfreq else defaultfreq maxopt = int(args.maxopt) + mod = 'orig' # until memory integrated if args.freqsweep: sc = args.freqsweep config = args.version if args.version else 'rv32e' - freshStart() for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep - runSynth(config, tech, freq, maxopt) + runSynth(config, mod, tech, freq, maxopt) if args.configsweep: - freshStart() - for config in ['rv32gc', 'rv32ic', 'rv64gc', 'rv64ic', 'rv32e']: # configs - config = config + '_orig' # until memory integrated - runSynth(config, tech, freq, maxopt) + for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32ic', 'rv32e']: #configs + runSynth(config, mod, tech, freq, maxopt) if args.featuresweep: - freshStart() - v = args.version if args.version else 'rv64gc' - for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations - config = v + '_' + mod - runSynth(config, tech, freq, maxopt) + config = args.version if args.version else 'rv64gc' + for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations 'orig', + runSynth(config, mod, tech, freq, maxopt) From 7004f262c9db2f84b00d5b09731f844d07dc32ad Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 26 Jan 2023 14:51:39 -0800 Subject: [PATCH 4/5] Added DWARF symbols for QEMU simulation --- examples/C/sum/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/C/sum/Makefile b/examples/C/sum/Makefile index 7c21cce23..a302309ff 100644 --- a/examples/C/sum/Makefile +++ b/examples/C/sum/Makefile @@ -4,7 +4,7 @@ $(TARGET).objdump: $(TARGET) riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump $(TARGET): $(TARGET).c Makefile - riscv64-unknown-elf-gcc -o $(TARGET) -g -O\ + riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\ -march=rv64gc -mabi=lp64d -mcmodel=medany \ -nostdlib -static -lm -fno-tree-loop-distribute-patterns \ -T../common/test.ld -I../common \ From 5df4679bcb8ecfa0a683f574eaf2d55d578d9fb6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 26 Jan 2023 14:53:25 -0800 Subject: [PATCH 5/5] Removed old link to imperas-riscv-tests --- addins/imperas-riscv-tests | 1 - 1 file changed, 1 deletion(-) delete mode 120000 addins/imperas-riscv-tests diff --git a/addins/imperas-riscv-tests b/addins/imperas-riscv-tests deleted file mode 120000 index c3f365a40..000000000 --- a/addins/imperas-riscv-tests +++ /dev/null @@ -1 +0,0 @@ -/opt/riscv/imperas-riscv-tests/ \ No newline at end of file