diff --git a/wally-pipelined/regression/wally-privileged.do b/wally-pipelined/regression/wally-privileged.do new file mode 100644 index 000000000..d969e6728 --- /dev/null +++ b/wally-pipelined/regression/wally-privileged.do @@ -0,0 +1,63 @@ +# wally-pipelined.do +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with Testbench +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +# Use this wally-pipelined.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally-pipelined.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-pipelined.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +# default to config/rv64ic, but allow this to be overridden at the command line. For example: +# do wally-pipelined.do ../config/rv32ic +switch $argc { + 0 {vlog +incdir+../config/rv64ic ../testbench/testbench-privileged.sv ../src/*/*.sv -suppress 2583} + 1 {vlog +incdir+$1 ../testbench/testbench-privileged.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583} +} +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +vopt +acc work.testbench -o workopt +vsim workopt + + +view wave + +-- display input and output signals as hexidecimal values +do ./wave-dos/default-waves.do + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {100 ps} +configure wave -namecolwidth 250 +configure wave -valuecolwidth 140 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +set DefaultRadix hexadecimal + +-- Run the Simulation +#run 4100 +run -all +#quit diff --git a/wally-pipelined/testbench/testbench-privileged.sv b/wally-pipelined/testbench/testbench-privileged.sv index 999604480..f8c519bce 100644 --- a/wally-pipelined/testbench/testbench-privileged.sv +++ b/wally-pipelined/testbench/testbench-privileged.sv @@ -1,12 +1,11 @@ /////////////////////////////////////////// -// testbench-privileged.sv +// testbench-imperas.sv // -// Written: Ben Bracker (bbracker@hmc.edu) 11 Feb. 2021, Tiny Modifications: Domenico Ottolia (dottolia@hmc.edu) 16 Mar. 2021 -// Based on: testbench-imperas.sv by David Harris +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: // // Purpose: Wally Testbench and helper modules -// Applies test programs meant to test peripherals -// These tests assume the processor itself is already working! +// Applies test programs from the Imperas suite // // A component of the Wally configurable RISC-V project. // @@ -28,6 +27,9 @@ `include "wally-config.vh" module testbench(); + parameter DEBUG = 0; + parameter TESTSBP = 0; + logic clk; logic reset; @@ -36,13 +38,13 @@ module testbench(); logic [`XLEN-1:0] signature[0:10000]; logic [`XLEN-1:0] testadr; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; - logic [31:0] InstrW; + //logic [31:0] InstrW; logic [`XLEN-1:0] meminit; - + //string tests64i[] = string tests[] = '{ - "rv64p/WALLY-CAUSE", "0" - }; - + "rv64p/WALLY-CAUSE", "4000" + }; + string ProgramAddrMapFile, ProgramLabelMapFile; logic [`AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; logic [31:0] HADDR; @@ -57,9 +59,26 @@ module testbench(); // pick tests based on modes supported - // *** actually I no longer support this - // would need to put this back in if you wanted to test anything other than rv64i - + //initial + // if (`XLEN == 64) begin // RV64 + // if(TESTSBP) begin + // tests = testsBP64; + // end else begin + // tests = {tests64i}; + // if (`C_SUPPORTED) tests = {tests, tests64ic}; + // else tests = {tests, tests64iNOc}; + // if (`M_SUPPORTED) tests = {tests, tests64m}; + // if (`A_SUPPORTED) tests = {tests, tests64a}; + // end + // // tests = {tests64a, tests}; + // end else begin // RV32 + // // *** add the 32 bit bp tests + // tests = {tests32i}; + // if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic}; + // else tests = {tests, tests32iNOc}; + // if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m}; + // if (`A_SUPPORTED) tests = {tests, tests32a}; + // end string signame, memfilename; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; @@ -75,10 +94,10 @@ module testbench(); wallypipelinedsoc dut(.*); // Track names of instructions - instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, - dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, - dut.hart.ifu.InstrM, InstrW, - InstrDName, InstrEName, InstrMName, InstrWName); + instrTrackerTBPriv it(clk, reset, dut.hart.ieu.dp.FlushE, + dut.hart.ifu.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, + dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, + InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests initial @@ -97,7 +116,10 @@ module testbench(); memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); - reset = 1; # 22; reset = 0; + ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"}; + ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"}; + $display("Read memfile %s", memfilename); + reset = 1; # 42; reset = 0; end // generate clock to sequence tests @@ -170,25 +192,43 @@ module testbench(); $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); $display("Read memfile %s", memfilename); + ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"}; + ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"}; reset = 1; # 17; reset = 0; end end - end + end // always @ (negedge clk) + + // track the current function or global label + if (DEBUG == 1) begin : functionRadix + function_radix function_radix(.reset(reset), + .ProgramAddrMapFile(ProgramAddrMapFile), + .ProgramLabelMapFile(ProgramLabelMapFile)); + end + + // initialize the branch predictor + initial begin + $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory); + $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory); + end + endmodule /* verilator lint_on STMTDLY */ /* verilator lint_on WIDTH */ -module instrTrackerTB( +module instrTrackerTBPriv( input logic clk, reset, FlushE, - input logic [31:0] InstrD, + input logic [31:0] InstrF, InstrD, input logic [31:0] InstrE, InstrM, - output logic [31:0] InstrW, - output string InstrDName, InstrEName, InstrMName, InstrWName); + input logic [31:0] InstrW, +// output logic [31:0] InstrW, + output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // stage Instr to Writeback for visualization - flopr #(32) InstrWReg(clk, reset, InstrM, InstrW); + // flopr #(32) InstrWReg(clk, reset, InstrM, InstrW); + instrNameDecTB fdec(InstrF, InstrFName); instrNameDecTB ddec(InstrD, InstrDName); instrNameDecTB edec(InstrE, InstrEName); instrNameDecTB mdec(InstrM, InstrMName); @@ -247,10 +287,18 @@ module instrNameDecTB( else name = "ILLEGAL"; 10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW"; else if (funct7 == 7'b0100000) name = "SUBW"; + else if (funct7 == 7'b0000001) name = "MULW"; + else name = "ILLEGAL"; + 10'b0111011_001: if (funct7 == 7'b0000000) name = "SLLW"; + else if (funct7 == 7'b0000001) name = "DIVW"; else name = "ILLEGAL"; - 10'b0111011_001: name = "SLLW"; 10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW"; else if (funct7 == 7'b0100000) name = "SRAW"; + else if (funct7 == 7'b0000001) name = "DIVUW"; + else name = "ILLEGAL"; + 10'b0111011_110: if (funct7 == 7'b0000001) name = "REMW"; + else name = "ILLEGAL"; + 10'b0111011_111: if (funct7 == 7'b0000001) name = "REMUW"; else name = "ILLEGAL"; 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD"; else if (funct7 == 7'b0000001) name = "MUL"; @@ -263,10 +311,10 @@ module instrNameDecTB( else if (funct7 == 7'b0000001) name = "MULHSU"; else name = "ILLEGAL"; 10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU"; - else if (funct7 == 7'b0000001) name = "DIV"; + else if (funct7 == 7'b0000001) name = "MULHU"; else name = "ILLEGAL"; 10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR"; - else if (funct7 == 7'b0000001) name = "MUL"; + else if (funct7 == 7'b0000001) name = "DIV"; else name = "ILLEGAL"; 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL"; else if (funct7 == 7'b0000001) name = "DIVU"; @@ -299,6 +347,30 @@ module instrNameDecTB( 10'b1110011_101: name = "CSRRWI"; 10'b1110011_110: name = "CSRRSI"; 10'b1110011_111: name = "CSRRCI"; + 10'b0101111_010: if (funct7[6:2] == 5'b00010) name = "LR.W"; + else if (funct7[6:2] == 5'b00011) name = "SC.W"; + else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.W"; + else if (funct7[6:2] == 5'b00000) name = "AMOADD.W"; + else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.W"; + else if (funct7[6:2] == 5'b01100) name = "AMOAND.W"; + else if (funct7[6:2] == 5'b01000) name = "AMOOR.W"; + else if (funct7[6:2] == 5'b10000) name = "AMOMIN.W"; + else if (funct7[6:2] == 5'b10100) name = "AMOMAX.W"; + else if (funct7[6:2] == 5'b11000) name = "AMOMINU.W"; + else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.W"; + else name = "ILLEGAL"; + 10'b0101111_011: if (funct7[6:2] == 5'b00010) name = "LR.D"; + else if (funct7[6:2] == 5'b00011) name = "SC.D"; + else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.D"; + else if (funct7[6:2] == 5'b00000) name = "AMOADD.D"; + else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.D"; + else if (funct7[6:2] == 5'b01100) name = "AMOAND.D"; + else if (funct7[6:2] == 5'b01000) name = "AMOOR.D"; + else if (funct7[6:2] == 5'b10000) name = "AMOMIN.D"; + else if (funct7[6:2] == 5'b10100) name = "AMOMAX.D"; + else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D"; + else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D"; + else name = "ILLEGAL"; 10'b0001111_???: name = "FENCE"; default: name = "ILLEGAL"; endcase diff --git a/wally-pipelined/testgen/privileged/testgen-CAUSE.py b/wally-pipelined/testgen/privileged/testgen-CAUSE.py index 4bd649622..7983783e5 100644 --- a/wally-pipelined/testgen/privileged/testgen-CAUSE.py +++ b/wally-pipelined/testgen/privileged/testgen-CAUSE.py @@ -1,8 +1,8 @@ #!/usr/bin/python3 ################################## -# testgen-CAUSE.py +# testgen-ADD-SUB.py # -# dottolia@hmc.edu 16 Mar 2021 +# ushakya@hmc.edu & dottolia@hmc.edu 14 Feb 2021 # # Generate directed and random test vectors for RISC-V Design Validation. ################################## @@ -13,7 +13,6 @@ from datetime import datetime from random import randint from random import seed -from enum import Enum from random import getrandbits ################################## @@ -30,160 +29,85 @@ from random import getrandbits # # exit(1) def randRegs(): - reg1 = randint(1,30) - reg2 = randint(1,30) - reg3 = randint(1,30) + reg1 = randint(1,31) + reg2 = randint(1,31) + reg3 = randint(1,31) if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2): return randRegs() else: return reg1, reg2, reg3 -def writeVectors(storecmd): +def writeVector(a, b, storecmd): global testnum + #expected = computeExpected(a, b, test) + #expected = expected % 2**xlen # drop carry if necessary + #if (expected < 0): # take twos complement + # expected = 2**xlen + expected + csr = "mscratch" + reg1, reg2, reg3 = randRegs() + lines = "\n# Testcase " + str(testnum) + ": " + csr + "\n" + lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" + lines = lines + "li x" + str(reg2) + ", MASK_XLEN(0)\n" - # t5 gets written with mtvec? + # Page 6 of unpriviledged spec + # For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects - # lines = f""" + expected = a - # li x{reg1}, 0 - # csrwi mtvec, 80002000 - # .data 00000000 - # j _done{testnum} + if test == "csrrw": + lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" + lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" - # _trap{testnum}: - # csrrs x{reg1}, mcause, x0 - # ecall + elif test == "csrrs": # at some point, try writing a non-zero value first + lines += "csrrw x0, " + csr + ", x0\n" # set csr to 0 - # _done{testnum}: - # add x0, x0, x0 - # """ + lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" + lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" + elif test == "csrrc": # at some point, try writing a non-one value first + allOnes = "0xFFFFFFFF" if xlen == 32 else "0xFFFFFFFFFFFFFFFF" - #lines = + lines += "li x" + str(reg1) + ", MASK_XLEN(" + allOnes + ")\n" + lines += "csrrw x0, " + csr + ", x" + str(reg1) + "\n" # set csr to all ones + + lines += "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" + + lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" + lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" + + expected = a ^ 0xFFFFFFFF if xlen == 32 else a ^ 0xFFFFFFFFFFFFFFFF + elif test == "csrrwi": + a = a & 0x1F # imm is only 5 bits + + lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n" + lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n" + + expected = a + elif test == "csrrsi": # at some point, try writing a non-zero value first + a = a & 0x1F + + lines += "csrrw x0, " + csr + ", x0\n" # set csr to 0 + + lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n" + lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n" + + expected = a + elif test == "csrrci": # at some point, try writing a non-one value first + a = a & 0x1F + allOnes = "0xFFFFFFFF" if xlen == 32 else "0xFFFFFFFFFFFFFFFF" + + lines += "li x" + str(reg1) + ", MASK_XLEN(" + allOnes + ")\n" + lines += "csrrw x0, " + csr + ", x" + str(reg1) + "\n" # set csr to all ones + + lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n" + lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n" + + expected = a ^ 0xFFFFFFFF if xlen == 32 else a ^ 0xFFFFFFFFFFFFFFFF - # https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html - - lines = f""" - j _setup - csrrs x31, mcause, x0 - csrrs x30, mepc, x0 - addi x30, x30, 0x100 - csrrw x0, mepc, x30 - mret - - _setup: - li x2, 0x80000004 - csrrw x0, mtvec, x2 - - """ + lines += storecmd + " x" + str(reg2) + ", " + str(wordsize*testnum) + "(x6)\n" + lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n" f.write(lines) - - # # User Software Interrupt - # write(f""" - # li x3, 0x8000000 - # {storecmd} x2, 0(x3) - # """, storecmd, True, 0, "u") - - # # A supervisor-level software interrupt is triggered on the current hart by writing 1 to its supervisor software interrupt-pending (SSIP) bit in the sip register. - # # page 58 of priv spec - # # Supervisor Software Interrupt - # write(f""" - # li x3, 0x8000000 - # {storecmd} x2, 0(x3) - # """, storecmd, True, 0, "s") - - # # Machine Software Interrupt - # write(f""" - # li x3, 0x8000000 - # {storecmd} x2, 0(x3) - # """, storecmd, True, 3) - - # User Timer Interrupt - #write(f""" - # lw x2, mtimecmp - # {storecmd} x2, mtimecmp - #""", storecmd, True, 4, "u") - - # # Supervisor Timer Interrupt - #write(f""" - # lw x2, mtimecmp - # {storecmd} x2, mtimecmp - #""", storecmd, True, 5, "s") - - # Machine Timer Interrupt - #write(f""" - # lw x2, mtimecmp - # {storecmd} x2, mtimecmp - #""", storecmd, True, 6) - - # User external interrupt True, 8 - # Supervisor external interrupt True, 9 - - # Instr Addr Misalign - write(f""" - li x2, 0x00000000 - lw x3, 11(x2) - """, storecmd, False, 0) - - # Instr Access Fault False, 1 - # Not possible in machine mode, because we can access all memory - - # Illegal Instruction - # . fill 1, 2, 0 outputs all 0s - write(f""" - .fill 1, 2, 0 - """, storecmd, False, 2) - - # Breakpoint - write(f""" - ebreak - """, storecmd, False, 3) - - # Load Addr Misalign - write(f""" - li x2, 0x00000000 - lw x3, 11(x2) - """, storecmd, False, 4) - - # Load Access Fault False, 5 - # Not possible in machine mode, because we can access all memory - - - # Store/AMO address misaligned - write(f""" - li x2, 0x00000000 - {storecmd} x3, 11(x2) - """, storecmd, False, 6) - - # Store/AMO access fault False, 7 - # Not possible in machine mode, because we can access all memory - - # Environment call from U-mode - # Environment call from S-mode - -def write(lines, storecmd, interrupt, code, mode = "m"): - global testnum - - # generate expected interrupt code - expected = (0 if not interrupt else (2**31 if xlen == 32 else 2**63)) + code - - lines = f""" - # Testcase {testnum} - li x31, 0 - {lines} - - {storecmd} x31, {str(wordsize*testnum)}(x6) - # RVTEST_IO_ASSERT_GPR_EQ(x0, 0, {formatstr.format(expected)}) - """ - - #if mode == "s": - # go to supervisor mode - #elif mode == "u": - # go to user mode - - f.write(lines) - if (xlen == 32): line = formatrefstr.format(expected)+"\n" else: @@ -195,38 +119,15 @@ def write(lines, storecmd, interrupt, code, mode = "m"): # main body ################################## -# name: (interrupt?, code) -# tests = { -# 'User software interrupt': (1, '0'), -# 'Supervisor software interrupt': (1, '1'), -# 'Machine software interrupt': (1, '3'), -# 'User timer interrupt': (1, '4'), -# 'Supervisor timer interrupt': (1, '5'), -# 'Machine timer interrupt': (1, '7'), -# 'User external interrupt': (1, '8'), -# 'Supervisor external interrupt': (1, '9'), -# 'Machine external interrupt': (1, '11'), -# 'Instruction address misaligned': (0, '0'), -# 'Instruction access fault': (0, '1'), -# 'Illegal instruction': (0, '2'), -# 'Breakpoint': (0, '3'), -# 'Load address misaligned': (0, '4'), -# 'Load access fault': (0, '5'), -# 'Store/AMO address misaligned': (0, '6'), -# 'Store/AMO access fault': (0, '7'), -# 'Environment call from U-mode': (0, '8'), -# 'Environment call from S-mode': (0, '9'), -# 'Environment call from M-mode': (0, '11'), -# 'Instruction page fault': (0, '12'), -# 'Load page fault': (0, '13'), -# 'Store/AMO page fault': (0, '15'), -# } -author = "Domenico Ottolia (dottolia@hmc.edu)" +# change these to suite your tests +# csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci +tests = ["csrrw"] +author = "ushakya@hmc.edu & dottolia@hmc.edu" xlens = [32, 64] numrand = 60; # setup -seed(0xC395DDEB9173AD42) # make tests reproducible +seed(0xC365DDEB9173AB42) # make tests reproducible # generate files for each test for xlen in xlens: @@ -239,41 +140,51 @@ for xlen in xlens: else: storecmd = "sd" wordsize = 8 + for test in tests: + corners = [ + 0, 1, 2, 0x1E, 0x1F, 0xFF, + 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, + 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1 + ] + imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/" + basename = "WALLY-CAUSE" + fname = imperaspath + "src/" + basename + ".S" + refname = imperaspath + "references/" + basename + ".reference_output" + testnum = 0 - imperaspath = f"""../../../imperas-riscv-tests/riscv-test-suite/rv{xlen}p/""" - basename = "WALLY-CAUSE" - fname = imperaspath + "src/" + basename + ".S" - refname = imperaspath + "references/" + basename + ".reference_output" - testnum = 0 + # print custom header part + f = open(fname, "w") + r = open(refname, "w") + line = "///////////////////////////////////////////\n" + f.write(line) + lines="// "+fname+ "\n// " + author + "\n" + f.write(lines) + line ="// Created " + str(datetime.now()) + f.write(line) - # print custom header part - f = open(fname, "w") - r = open(refname, "w") - line = "///////////////////////////////////////////\n" - f.write(line) - lines="// "+fname+ "\n// " + author + "\n" - f.write(lines) - line ="// Created " + str(datetime.now()) - f.write(line) + # insert generic header + h = open("../testgen_header.S", "r") + for line in h: + f.write(line) - # insert generic header - # h = open("../testgen_header.S", "r") - # for line in h: - # f.write(line) - - # print directed and random test vectors - writeVectors(storecmd) + # print directed and random test vectors + for a in corners: + for b in corners: + writeVector(a, b, storecmd) + for i in range(0,numrand): + a = getrandbits(xlen) + b = getrandbits(xlen) + writeVector(a, b, storecmd) - # print footer - # h = open("../testgen_footer.S", "r") - # for line in h: - # f.write(line) - - # Finish - # lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" - # lines = lines + "\nRV_COMPLIANCE_DATA_END\n" - # f.write(lines) - f.close() - r.close() + # print footer + h = open("../testgen_footer.S", "r") + for line in h: + f.write(line) + # Finish + lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" + lines = lines + "\nRV_COMPLIANCE_DATA_END\n" + f.write(lines) + f.close() + r.close() \ No newline at end of file