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fixed bugs

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This commit is contained in:
Shreya Sanghai 2021-03-04 12:59:45 -05:00
parent 7cd8f1a592
commit f95a1eadd9
1 changed files with 67 additions and 45 deletions
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112
wally-pipelined/src/privileged/csrc.sv
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@ -49,7 +49,7 @@ module csrc (
for (i=0; i<= `COUNTERS; i = i+1) begin for (i=0; i<= `COUNTERS; i = i+1) begin
if (i !==1) begin if (i !==1) begin
MHPMCOUNTER[i] = 12'hB00 + i; // not sure this addition is legit MHPMCOUNTER[i] = 12'hB00 + i; // not sure this addition is legit
MHPMCOUNTERH[i] = 12'hB83 + i; MHPMCOUNTERH[i] = 12'hB80 + i;
HPMCOUNTER[i] = 12'hC00 + i; HPMCOUNTER[i] = 12'hC00 + i;
HPMCOUNTERH[i] = 12'hC80 + i; HPMCOUNTERH[i] = 12'hC80 + i;
MHPEVENT[i] = 12'h320 + i; // MHPEVENT[0] = MCOUNTERINHIBIT MHPEVENT[i] = 12'h320 + i; // MHPEVENT[0] = MCOUNTERINHIBIT
@ -73,6 +73,8 @@ module csrc (
logic [`COUNTERS:0] WriteHPMCOUNTERM; logic [`COUNTERS:0] WriteHPMCOUNTERM;
logic [4:0] CounterNumM; logic [4:0] CounterNumM;
assign CounterNumM = CSRAdrM[4:0]; // which counter to read? ***
for (j=0; j<= `COUNTERS; j = j+1) begin for (j=0; j<= `COUNTERS; j = j+1) begin
// Write enables // Write enables
if (j !==1) begin if (j !==1) begin
@ -100,62 +102,82 @@ module csrc (
flopr #(32) HPMCOUNTERreg_j(clk, reset, NextHPMCOUNTERM[j], HPMCOUNTER_REGW[j][31:0]); flopr #(32) HPMCOUNTERreg_j(clk, reset, NextHPMCOUNTERM[j], HPMCOUNTER_REGW[j][31:0]);
flopr #(32) HPMCOUNTERHreg_j(clk, reset, NextHPMCOUNTERHM[j], HPMCOUNTER_REGW[j][63:32]); flopr #(32) HPMCOUNTERHreg_j(clk, reset, NextHPMCOUNTERHM[j], HPMCOUNTER_REGW[j][63:32]);
end end
end // end for
// eventually move TIME and TIMECMP to the CLINT // eventually move TIME and TIMECMP to the CLINT
// run TIME off asynchronous reference clock // run TIME off asynchronous reference clock
// synchronize write enable to TIME // synchronize write enable to TIME
// four phase handshake to synchronize reads from TIME // four phase handshake to synchronize reads from TIME
// interrupt on timer compare // interrupt on timer compare
// ability to disable optional CSRs // ability to disable optional CSRs
// Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags // Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags
assign CounterNumM = CSRAdrM[4:0]; // which counter to read? *** if (`XLEN==64) begin // 64-bit counter reads
if (`XLEN==64) begin // 64-bit counter reads always_comb
always_comb if (PrivilegeModeW == `M_MODE ||
if (PrivilegeModeW == `M_MODE || MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
IllegalCSRCAccessM = 0; if (CSRAdrM[11:5] == MHPMCOUNTER[0][11:5] || CSRAdrM[11:5] == HPMCOUNTER[0][11:5]) begin
case (CSRAdrM) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM[4:0]];
MHPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j]; IllegalCSRCAccessM = 0;
HPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j];
default: begin
CSRCReadValM = 0;
IllegalCSRCAccessM = 1;
end
endcase
end end
// //case (CSRAdrM)
// MHPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j];
// HPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j];
// default: begin
// CSRCReadValM = 0;
// IllegalCSRCAccessM = 1;
// end
// endcase
// end
else begin else begin
IllegalCSRCAccessM = 1; // no privileges for this csr IllegalCSRCAccessM = 1; // no privileges for this csr
CSRCReadValM = 0; CSRCReadValM = 0;
end end
end
else begin
IllegalCSRCAccessM = 1; // no privileges for this csr
CSRCReadValM = 0;
end end
else begin // 32-bit counter reads end
always_comb else begin // 32-bit counter reads
if (PrivilegeModeW == `M_MODE || always_comb
MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin if (PrivilegeModeW == `M_MODE ||
IllegalCSRCAccessM = 0; MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
case (CSRAdrM)
MHPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j][31:0]; if (CSRAdrM[11:5] == MHPMCOUNTER[0][11:5] || CSRAdrM[11:5] == HPMCOUNTER[0][11:5] ||
HPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j][31:0]; CSRAdrM[11:5] == MHPMCOUNTERH[0][11:5] || CSRAdrM[11:5] == HPMCOUNTERH[0][11:5]) begin
MHPMCOUNTERH[j]: CSRCReadValM = HPMCOUNTER_REGW[j][63:32]; CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM[4:0]];
HPMCOUNTERH[j]: CSRCReadValM = HPMCOUNTER_REGW[j][63:32]; IllegalCSRCAccessM = 0;
default: begin
CSRCReadValM = 0;
IllegalCSRCAccessM = 1;
end
endcase
end end
else begin else begin
IllegalCSRCAccessM = 1; // no privileges for this csr IllegalCSRCAccessM = 1; // no privileges for this csr
CSRCReadValM = 0; CSRCReadValM = 0;
end end
end // 32-bit counter end
end // end for loop // IllegalCSRCAccessM = 0;
end // end for if // case (CSRAdrM)
// MHPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j][31:0];
// HPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j][31:0];
// MHPMCOUNTERH[j]: CSRCReadValM = HPMCOUNTER_REGW[j][63:32];
// HPMCOUNTERH[j]: CSRCReadValM = HPMCOUNTER_REGW[j][63:32];
// default: begin
// CSRCReadValM = 0;
// IllegalCSRCAccessM = 1;
// end
// endcase
end
else begin
IllegalCSRCAccessM = 1; // no privileges for this csr
CSRCReadValM = 0;
end
end // 32-bit counter end
end // end for big if
else begin else begin
assign CSRCReadValM = 0; assign CSRCReadValM = 0;
assign IllegalCSRCAccessM = 1; assign IllegalCSRCAccessM = 1;
end // end for else end // end for else
endgenerate endgenerate
endmodule endmodule