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https://github.com/openhwgroup/cvw
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fixed bugs
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@ -49,7 +49,7 @@ module csrc (
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for (i=0; i<= `COUNTERS; i = i+1) begin
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for (i=0; i<= `COUNTERS; i = i+1) begin
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if (i !==1) begin
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if (i !==1) begin
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MHPMCOUNTER[i] = 12'hB00 + i; // not sure this addition is legit
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MHPMCOUNTER[i] = 12'hB00 + i; // not sure this addition is legit
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MHPMCOUNTERH[i] = 12'hB83 + i;
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MHPMCOUNTERH[i] = 12'hB80 + i;
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HPMCOUNTER[i] = 12'hC00 + i;
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HPMCOUNTER[i] = 12'hC00 + i;
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HPMCOUNTERH[i] = 12'hC80 + i;
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HPMCOUNTERH[i] = 12'hC80 + i;
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MHPEVENT[i] = 12'h320 + i; // MHPEVENT[0] = MCOUNTERINHIBIT
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MHPEVENT[i] = 12'h320 + i; // MHPEVENT[0] = MCOUNTERINHIBIT
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@ -73,6 +73,8 @@ module csrc (
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logic [`COUNTERS:0] WriteHPMCOUNTERM;
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logic [`COUNTERS:0] WriteHPMCOUNTERM;
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logic [4:0] CounterNumM;
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logic [4:0] CounterNumM;
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assign CounterNumM = CSRAdrM[4:0]; // which counter to read? ***
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for (j=0; j<= `COUNTERS; j = j+1) begin
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for (j=0; j<= `COUNTERS; j = j+1) begin
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// Write enables
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// Write enables
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if (j !==1) begin
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if (j !==1) begin
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@ -100,62 +102,82 @@ module csrc (
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flopr #(32) HPMCOUNTERreg_j(clk, reset, NextHPMCOUNTERM[j], HPMCOUNTER_REGW[j][31:0]);
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flopr #(32) HPMCOUNTERreg_j(clk, reset, NextHPMCOUNTERM[j], HPMCOUNTER_REGW[j][31:0]);
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flopr #(32) HPMCOUNTERHreg_j(clk, reset, NextHPMCOUNTERHM[j], HPMCOUNTER_REGW[j][63:32]);
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flopr #(32) HPMCOUNTERHreg_j(clk, reset, NextHPMCOUNTERHM[j], HPMCOUNTER_REGW[j][63:32]);
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end
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end
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end // end for
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// eventually move TIME and TIMECMP to the CLINT
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// eventually move TIME and TIMECMP to the CLINT
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// run TIME off asynchronous reference clock
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// run TIME off asynchronous reference clock
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// synchronize write enable to TIME
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// synchronize write enable to TIME
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// four phase handshake to synchronize reads from TIME
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// four phase handshake to synchronize reads from TIME
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// interrupt on timer compare
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// interrupt on timer compare
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// ability to disable optional CSRs
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// ability to disable optional CSRs
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// Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags
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// Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags
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assign CounterNumM = CSRAdrM[4:0]; // which counter to read? ***
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if (`XLEN==64) begin // 64-bit counter reads
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if (`XLEN==64) begin // 64-bit counter reads
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always_comb
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always_comb
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if (PrivilegeModeW == `M_MODE ||
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if (PrivilegeModeW == `M_MODE ||
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MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
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MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
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IllegalCSRCAccessM = 0;
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if (CSRAdrM[11:5] == MHPMCOUNTER[0][11:5] || CSRAdrM[11:5] == HPMCOUNTER[0][11:5]) begin
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case (CSRAdrM)
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CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM[4:0]];
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MHPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j];
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IllegalCSRCAccessM = 0;
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HPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j];
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default: begin
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1;
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end
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endcase
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end
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end
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// //case (CSRAdrM)
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// MHPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j];
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// HPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j];
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// default: begin
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// CSRCReadValM = 0;
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// IllegalCSRCAccessM = 1;
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// end
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// endcase
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// end
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else begin
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else begin
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IllegalCSRCAccessM = 1; // no privileges for this csr
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IllegalCSRCAccessM = 1; // no privileges for this csr
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CSRCReadValM = 0;
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CSRCReadValM = 0;
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end
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end
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end
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else begin
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IllegalCSRCAccessM = 1; // no privileges for this csr
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CSRCReadValM = 0;
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end
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end
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else begin // 32-bit counter reads
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end
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always_comb
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else begin // 32-bit counter reads
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if (PrivilegeModeW == `M_MODE ||
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always_comb
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MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
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if (PrivilegeModeW == `M_MODE ||
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IllegalCSRCAccessM = 0;
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MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
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case (CSRAdrM)
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MHPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j][31:0];
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if (CSRAdrM[11:5] == MHPMCOUNTER[0][11:5] || CSRAdrM[11:5] == HPMCOUNTER[0][11:5] ||
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HPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j][31:0];
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CSRAdrM[11:5] == MHPMCOUNTERH[0][11:5] || CSRAdrM[11:5] == HPMCOUNTERH[0][11:5]) begin
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MHPMCOUNTERH[j]: CSRCReadValM = HPMCOUNTER_REGW[j][63:32];
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CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM[4:0]];
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HPMCOUNTERH[j]: CSRCReadValM = HPMCOUNTER_REGW[j][63:32];
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IllegalCSRCAccessM = 0;
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default: begin
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1;
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end
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endcase
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end
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end
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else begin
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else begin
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IllegalCSRCAccessM = 1; // no privileges for this csr
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IllegalCSRCAccessM = 1; // no privileges for this csr
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CSRCReadValM = 0;
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CSRCReadValM = 0;
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end
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end
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end // 32-bit counter end
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end // end for loop
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// IllegalCSRCAccessM = 0;
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end // end for if
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// case (CSRAdrM)
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// MHPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j][31:0];
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// HPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j][31:0];
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// MHPMCOUNTERH[j]: CSRCReadValM = HPMCOUNTER_REGW[j][63:32];
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// HPMCOUNTERH[j]: CSRCReadValM = HPMCOUNTER_REGW[j][63:32];
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// default: begin
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// CSRCReadValM = 0;
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// IllegalCSRCAccessM = 1;
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// end
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// endcase
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end
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else begin
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IllegalCSRCAccessM = 1; // no privileges for this csr
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CSRCReadValM = 0;
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end
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end // 32-bit counter end
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end // end for big if
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else begin
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else begin
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assign CSRCReadValM = 0;
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assign CSRCReadValM = 0;
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assign IllegalCSRCAccessM = 1;
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assign IllegalCSRCAccessM = 1;
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end // end for else
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end // end for else
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endgenerate
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endgenerate
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endmodule
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endmodule
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