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merge cleanup; mem init is broken

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bbracker 2021-04-26 08:00:17 -04:00
parent 7947858481
commit f921886451
2 changed files with 4 additions and 4 deletions
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1
wally-pipelined/src/ifu/ifu.sv
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@ -81,7 +81,6 @@ module ifu (
logic [31:0] InstrRawD, InstrE, InstrW; logic [31:0] InstrRawD, InstrE, InstrW;
localparam [31:0] nop = 32'h00000013; // instruction for NOP localparam [31:0] nop = 32'h00000013; // instruction for NOP
logic reset_q; // *** look at this later. logic reset_q; // *** look at this later.
logic [`XLEN-1:0] PCPF;
logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;

5
wally-pipelined/testbench/testbench-imperas.sv
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@ -471,9 +471,10 @@ module testbench();
// the design. // the design.
if (`XLEN == 32) meminit = 32'hFEDC0123; if (`XLEN == 32) meminit = 32'hFEDC0123;
else meminit = 64'hFEDCBA9876543210; else meminit = 64'hFEDCBA9876543210;
for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin // *** broken because DTIM also drives RAM
/*for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
dut.uncore.dtim.RAM[i] = meminit; dut.uncore.dtim.RAM[i] = meminit;
end end*/
// read test vectors into memory // read test vectors into memory
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
$readmemh(memfilename, dut.uncore.dtim.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM);