diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 56f400a50..ad7deb76e 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -81,7 +81,6 @@ module ifu (
   logic [31:0]      InstrRawD, InstrE, InstrW;
   localparam [31:0]      nop = 32'h00000013; // instruction for NOP
   logic 	    reset_q; // *** look at this later.
-  logic [`XLEN-1:0] PCPF;
 
   logic 	    BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
   
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index 6ddb59e3b..c67e73a27 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -471,9 +471,10 @@ module testbench();
       // the design.
       if (`XLEN == 32) meminit = 32'hFEDC0123;
       else meminit = 64'hFEDCBA9876543210;
-      for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
-	dut.uncore.dtim.RAM[i] = meminit;
-      end
+      // *** broken because DTIM also drives RAM
+      /*for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
+	      dut.uncore.dtim.RAM[i] = meminit;
+      end*/
       // read test vectors into memory
       memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
       $readmemh(memfilename, dut.uncore.dtim.RAM);