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Updated uncore to use sdc.

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Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
This commit is contained in:
Ross Thompson 2021-10-25 14:07:44 -05:00
parent 6bad4058eb
commit f7583d0e0d
4 changed files with 16 additions and 14 deletions
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17
wally-pipelined/regression/fpga-wave.do
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@ -292,6 +292,10 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wally
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/SelAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/SelAdrM
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/ReadDataBlockM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/ReadDataBlockM
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/DCacheMemWriteData add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/DCacheMemWriteData
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/FlushWay
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/VictimDirty
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/VDWriteEnableWay
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/ClearDirty
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/SetValid} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/SetValid}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/SetDirty} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/SetDirty}
@ -600,17 +604,8 @@ add wave -noupdate -group other -expand -group response /testbench/dut/wallypipe
add wave -noupdate -group other -expand -group response /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_NO_ERROR_MASK add wave -noupdate -group other -expand -group response /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_NO_ERROR_MASK
add wave -noupdate -group other -expand -group response /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_NO_ERROR_ANS add wave -noupdate -group other -expand -group response /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_NO_ERROR_ANS
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_dat_fsm/i_DATA_CRC16_GOOD add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_dat_fsm/i_DATA_CRC16_GOOD
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/RAM
add wave -noupdate /testbench/dtim/RAM
add wave -noupdate /testbench/dtim/A
add wave -noupdate /testbench/dtim/HADDR
add wave -noupdate /testbench/dtim/HRESPTim
add wave -noupdate /testbench/dtim/HSELTim
add wave -noupdate /testbench/dtim/HWRITE
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/adrdecs/SelRegions
add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/HSELTim
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 6} {1090427 ns} 1} {{Cursor 3} {1157417 ns} 1} {{Cursor 4} {1156308 ns} 0} WaveRestoreCursors {{Cursor 6} {1090427 ns} 1} {{Cursor 3} {1157417 ns} 1} {{Cursor 4} {17457065 ns} 0}
quietly wave cursor active 3 quietly wave cursor active 3
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 297 configure wave -valuecolwidth 297
@ -626,4 +621,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {1156224 ns} {1156384 ns} WaveRestoreZoom {17456867 ns} {17457201 ns}

7
wally-pipelined/src/cache/dcache.sv vendored
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@ -153,6 +153,9 @@ module dcache
logic LRUWriteEn; logic LRUWriteEn;
logic [NUMWAYS-1:0] VDWriteEnableWay;
// Read Path CPU (IEU) side // Read Path CPU (IEU) side
mux4 #(INDEXLEN) mux4 #(INDEXLEN)
@ -178,7 +181,7 @@ module dcache
.WAdr, .WAdr,
.PAdr(MemPAdrM[`PA_BITS-1:0]), .PAdr(MemPAdrM[`PA_BITS-1:0]),
.WriteEnable(SRAMWayWriteEnable), .WriteEnable(SRAMWayWriteEnable),
.VDWriteEnable, .VDWriteEnable(VDWriteEnableWay),
.WriteWordEnable(SRAMWordEnable), .WriteWordEnable(SRAMWordEnable),
.TagWriteEnable(SRAMBlockWayWriteEnableM), .TagWriteEnable(SRAMBlockWayWriteEnableM),
.WriteData(SRAMWriteData), .WriteData(SRAMWriteData),
@ -340,6 +343,8 @@ module dcache
.d(NextFlushWay), .d(NextFlushWay),
.q(FlushWay)); .q(FlushWay));
assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}};
assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]}; assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1]; assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];

4
wally-pipelined/src/wally/wallypipelinedsoc.sv
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@ -105,6 +105,8 @@ module wallypipelinedsoc (
uncore uncore(.HCLK, .HRESETn, uncore uncore(.HCLK, .HRESETn,
.HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED,
.TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .MTIMECMP_CLINT .TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .MTIMECMP_CLINT,
.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK
); );
endmodule endmodule

2
wally-pipelined/testbench/testbench-fpga.sv
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@ -639,7 +639,7 @@ string tests32f[] = '{
// read test vectors into memory // read test vectors into memory
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
//romfilename = {"../../testsBP/fpga-test-sdc/bin/fpga-test-sdc.hex"}; //romfilename = {"../../testsBP/fpga-test-sdc/bin/fpga-test-sdc.hex"};
romfilename = {"../../testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; romfilename = {"../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
sdcfilename = {"../src/sdc/tb/ramdisk2.hex"}; sdcfilename = {"../src/sdc/tb/ramdisk2.hex"};
$readmemh(memfilename, dtim.RAM); $readmemh(memfilename, dtim.RAM);
$readmemh(romfilename, dut.wallypipelinedsoc.uncore.bootdtim.bootdtim.RAM); $readmemh(romfilename, dut.wallypipelinedsoc.uncore.bootdtim.bootdtim.RAM);