diff --git a/wally-pipelined/regression/fpga-wave.do b/wally-pipelined/regression/fpga-wave.do
index 1d0a3351a..02e357b4c 100644
--- a/wally-pipelined/regression/fpga-wave.do
+++ b/wally-pipelined/regression/fpga-wave.do
@@ -292,6 +292,10 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wally
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/SelAdrM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/ReadDataBlockM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/DCacheMemWriteData
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/FlushWay
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/VictimDirty
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/VDWriteEnableWay
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu/dcache/ClearDirty
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/WriteEnable}
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/SetValid}
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu/dcache/MemWay[0]/SetDirty}
@@ -600,17 +604,8 @@ add wave -noupdate -group other -expand -group response /testbench/dut/wallypipe
 add wave -noupdate -group other -expand -group response /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_NO_ERROR_MASK
 add wave -noupdate -group other -expand -group response /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_NO_ERROR_ANS
 add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_dat_fsm/i_DATA_CRC16_GOOD
-add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/RAM
-add wave -noupdate /testbench/dtim/RAM
-add wave -noupdate /testbench/dtim/A
-add wave -noupdate /testbench/dtim/HADDR
-add wave -noupdate /testbench/dtim/HRESPTim
-add wave -noupdate /testbench/dtim/HSELTim
-add wave -noupdate /testbench/dtim/HWRITE
-add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/adrdecs/SelRegions
-add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/HSELTim
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 6} {1090427 ns} 1} {{Cursor 3} {1157417 ns} 1} {{Cursor 4} {1156308 ns} 0}
+WaveRestoreCursors {{Cursor 6} {1090427 ns} 1} {{Cursor 3} {1157417 ns} 1} {{Cursor 4} {17457065 ns} 0}
 quietly wave cursor active 3
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 297
@@ -626,4 +621,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {1156224 ns} {1156384 ns}
+WaveRestoreZoom {17456867 ns} {17457201 ns}
diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index 22f9cd276..b06f40ca4 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -152,6 +152,9 @@ module dcache
   logic SelEvict;
 
   logic LRUWriteEn;
+
+  logic [NUMWAYS-1:0] VDWriteEnableWay;
+  
   
   // Read Path CPU (IEU) side
 
@@ -178,7 +181,7 @@ module dcache
 		      .WAdr,
 		      .PAdr(MemPAdrM[`PA_BITS-1:0]),
 		      .WriteEnable(SRAMWayWriteEnable),
-		      .VDWriteEnable,		      
+		      .VDWriteEnable(VDWriteEnableWay),		      
 		      .WriteWordEnable(SRAMWordEnable),
 		      .TagWriteEnable(SRAMBlockWayWriteEnableM), 
 		      .WriteData(SRAMWriteData),
@@ -340,6 +343,8 @@ module dcache
 	      .d(NextFlushWay),
 	      .q(FlushWay));
 
+  assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}};
+
   assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
 
   assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];
diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv
index 87b39533e..7f9ead99d 100644
--- a/wally-pipelined/src/wally/wallypipelinedsoc.sv
+++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv
@@ -105,6 +105,8 @@ module wallypipelinedsoc (
   uncore uncore(.HCLK, .HRESETn,
     .HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
     .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED,
-    .TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .MTIMECMP_CLINT
+    .TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .MTIMECMP_CLINT,
+		.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK
+		
 );
 endmodule
diff --git a/wally-pipelined/testbench/testbench-fpga.sv b/wally-pipelined/testbench/testbench-fpga.sv
index a5bd3df68..1c573988d 100644
--- a/wally-pipelined/testbench/testbench-fpga.sv
+++ b/wally-pipelined/testbench/testbench-fpga.sv
@@ -639,7 +639,7 @@ string tests32f[] = '{
       // read test vectors into memory
       memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
       //romfilename = {"../../testsBP/fpga-test-sdc/bin/fpga-test-sdc.hex"};
-      romfilename = {"../../testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
+      romfilename = {"../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
       sdcfilename = {"../src/sdc/tb/ramdisk2.hex"};      
       $readmemh(memfilename, dtim.RAM);
       $readmemh(romfilename, dut.wallypipelinedsoc.uncore.bootdtim.bootdtim.RAM);