From f08d5b23d59e30e11aedfcbbb7ae88085e04f3bc Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 21 Sep 2022 13:02:34 -0700 Subject: [PATCH 1/3] Eliminated store after store stall when no cache; simplified divshiftcalc logic. --- pipelined/regression/regression-wally | 2 +- pipelined/src/fpu/postproc/divshiftcalc.sv | 2 +- pipelined/src/ieu/controller.sv | 4 +++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 456ba8fe9..48dd7c26c 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -91,7 +91,7 @@ for test in tests32ic: grepstr="All tests ran without failures") configs.append(tc) -tests32i = ["wally32periph"] +tests32i = ["arch32i", "wally32periph"] for test in tests32i: tc = TestCase( name=test, diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv index ee8581a55..8e36ad88a 100644 --- a/pipelined/src/fpu/postproc/divshiftcalc.sv +++ b/pipelined/src/fpu/postproc/divshiftcalc.sv @@ -77,5 +77,5 @@ module divshiftcalc( // *** explain why radix 4 division needs a left shift by 1 // *** can this shift be moved into the shiftcorrection logic? assign PreDivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}}; - assign DivShiftIn = PreDivShiftIn << (`RADIX==4 & ~Sqrt); // {{`NF{1'b0}}, DivQm[`DIVb-1:0], {`NORMSHIFTSZ-`DIVb+2-`NF{1'b0}}}; + assign DivShiftIn = PreDivShiftIn << (`RADIX==4 & ~Sqrt); endmodule diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index d0b1e5fc2..ab623b0e5 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -236,5 +236,7 @@ module controller( // Stall pipeline at Fetch if a CSR Write or Fence is pending in the subsequent stages assign CSRWriteFencePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM | FencePendingD | FencePendingE | FencePendingM; - assign StoreStallD = MemRWE[0] & ((|MemRWD) | (|AtomicD)); + // the synchronous DTIM cannot read immediately after write + // a cache cannot read or write immediately after a write + assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE)) | (|AtomicD)); endmodule From fce927810af84d9d019ba14189e1e1c95e8a966b Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 21 Sep 2022 13:19:48 -0700 Subject: [PATCH 2/3] Fixed testbench-fp to support all again --- pipelined/testbench/testbench-fp.sv | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index 2b2627e9b..748be2280 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -104,6 +104,7 @@ module testbenchfp; logic DivDone; logic DivNegSticky; logic [`NE+1:0] DivCalcExp; + logic divsqrtop; /////////////////////////////////////////////////////////////////////////////////////////////// @@ -878,12 +879,16 @@ always @(negedge clk) begin // check if result is correct // - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) // if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((DivBusy===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin - assign ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx); - assign FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx); - assign CheckNow = (DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT); + ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx); + FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx); + divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL; + + //assign divsqrtop = OpCtrl[TestNum] == `SQRT_OPCTRL | OpCtrl[TestNum] == `DIV_OPCTRL; + CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT); if(~(ResMatch & FlagMatch) & CheckNow) begin // if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin errors += 1; + $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); $display("Error in %s", Tests[TestNum]); $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); $stop; From cfa83fdd98411b213ec52ce9a856c195c49f8e68 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 21 Sep 2022 13:30:35 -0700 Subject: [PATCH 3/3] For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc --- pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv | 2 +- pipelined/src/fpu/postproc/divshiftcalc.sv | 12 +++--------- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv index 5e1f27253..b0beae6d9 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -92,7 +92,7 @@ module fdivsqrtiter( logic [1:0] initCSqrt, initCDiv2, initCDiv4, initCUpper; assign initCSqrt = 2'b11; assign initCDiv2 = 2'b10; - assign initCDiv4 = 2'b10; // *** not sure why this works; seems like it should be 00 for initializing to -4 + assign initCDiv4 = 2'b00; // *** not sure why this works; seems like it should be 00 for initializing to -4 assign initCUpper = SqrtE ? initCSqrt : (`RADIX == 4) ? initCDiv4 : initCDiv2; assign initC = {initCUpper, {`DIVb{1'b0}}}; diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv index 8e36ad88a..8b6fc0936 100644 --- a/pipelined/src/fpu/postproc/divshiftcalc.sv +++ b/pipelined/src/fpu/postproc/divshiftcalc.sv @@ -42,11 +42,8 @@ module divshiftcalc( ); logic [`LOGNORMSHIFTSZ-1:0] NormShift, DivDenormShiftAmt; logic [`NE+1:0] DivDenormShift; - logic [`NORMSHIFTSZ-1:0] PreDivShiftIn; - - logic [`DURLEN-1:0] DivEarlyTermShift = 0; - - // is the result denromalized + + // is the result denormalized // if the exponent is 1 then the result needs to be normalized then the result is denormalizes assign DivResDenorm = DivQe[`NE+1]|(~|DivQe[`NE+1:0]); @@ -74,8 +71,5 @@ module divshiftcalc( assign DivDenormShiftAmt = DivDenormShiftPos ? DivDenormShift[`LOGNORMSHIFTSZ-1:0] : '0; assign DivShiftAmt = DivResDenorm ? DivDenormShiftAmt : NormShift; - // *** explain why radix 4 division needs a left shift by 1 - // *** can this shift be moved into the shiftcorrection logic? - assign PreDivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}}; - assign DivShiftIn = PreDivShiftIn << (`RADIX==4 & ~Sqrt); + assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}}; endmodule