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Just needed to recompile - all good. Now removed uretM because N-mode is depricated

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David Harris 2022-02-15 19:48:49 +00:00
parent 1326ade1a0
commit f734afb866
6 changed files with 11 additions and 18 deletions
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4
pipelined/src/privileged/csr.sv
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@ -42,7 +42,7 @@ module csr #(parameter
input logic StallE, StallM, StallW, input logic StallE, StallM, StallW,
input logic [31:0] InstrM, input logic [31:0] InstrM,
input logic [`XLEN-1:0] PCM, SrcAM, input logic [`XLEN-1:0] PCM, SrcAM,
input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM,
input logic TimerIntM, ExtIntM, SwIntM, input logic TimerIntM, ExtIntM, SwIntM,
input logic [63:0] MTIME_CLINT, input logic [63:0] MTIME_CLINT,
input logic InstrValidM, FRegWriteM, LoadStallD, input logic InstrValidM, FRegWriteM, LoadStallD,
@ -128,7 +128,7 @@ module csr #(parameter
csrsr csrsr(.clk, .reset, .StallW, csrsr csrsr(.clk, .reset, .StallW,
.WriteMSTATUSM, .WriteSSTATUSM, .WriteUSTATUSM, .WriteMSTATUSM, .WriteSSTATUSM, .WriteUSTATUSM,
.TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW, .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
.mretM, .sretM, .uretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM, .mretM, .sretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM,
.MSTATUS_REGW, .SSTATUS_REGW, .USTATUS_REGW, .MSTATUS_REGW, .SSTATUS_REGW, .USTATUS_REGW,
.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM); .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM);

5
pipelined/src/privileged/csrsr.sv
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@ -36,7 +36,7 @@ module csrsr (
input logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM, input logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM,
input logic TrapM, FRegWriteM, input logic TrapM, FRegWriteM,
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
input logic mretM, sretM, uretM, input logic mretM, sretM,
input logic WriteFRMM, WriteFFLAGSM, input logic WriteFRMM, WriteFFLAGSM,
input logic [`XLEN-1:0] CSRWriteValM, input logic [`XLEN-1:0] CSRWriteValM,
output logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW, output logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW,
@ -156,9 +156,6 @@ module csrsr (
STATUS_SPIE <= #1 `S_SUPPORTED; STATUS_SPIE <= #1 `S_SUPPORTED;
STATUS_SPP <= #1 0; // Privileged 4.1.1 STATUS_SPP <= #1 0; // Privileged 4.1.1
STATUS_MPRV_INT <= #1 0; // per 20210108 draft spec STATUS_MPRV_INT <= #1 0; // per 20210108 draft spec
end else if (uretM) begin
STATUS_UIE <= #1 STATUS_UPIE;
STATUS_UPIE <= #1 `U_SUPPORTED;
end else if (WriteMSTATUSM) begin end else if (WriteMSTATUSM) begin
STATUS_TSR_INT <= #1 CSRWriteValM[22]; STATUS_TSR_INT <= #1 CSRWriteValM[22];
STATUS_TW_INT <= #1 CSRWriteValM[21]; STATUS_TW_INT <= #1 CSRWriteValM[21];

5
pipelined/src/privileged/privdec.sv
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@ -37,12 +37,11 @@ module privdec (
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
input logic STATUS_TSR, input logic STATUS_TSR,
output logic IllegalInstrFaultM, output logic IllegalInstrFaultM,
output logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM); output logic sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM);
logic IllegalPrivilegedInstrM; logic IllegalPrivilegedInstrM;
// xRET defined in Privileged Spect 3.2.2 // xRET defined in Privileged Spect 3.2.2
assign uretM = PrivilegedM & (InstrM[31:20] == 12'b000000000010) & `N_SUPPORTED;
assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED & assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED &
PrivilegeModeW[0] & ~STATUS_TSR; PrivilegeModeW[0] & ~STATUS_TSR;
assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == `M_MODE); assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == `M_MODE);
@ -51,7 +50,7 @@ module privdec (
assign ebreakM = PrivilegedM & (InstrM[31:20] == 12'b000000000001); assign ebreakM = PrivilegedM & (InstrM[31:20] == 12'b000000000001);
assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101); assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101);
assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001); assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001);
assign IllegalPrivilegedInstrM = PrivilegedM & ~(uretM|sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM); assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | TrappedSRETM; // *** generalize this for other instructions assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | TrappedSRETM; // *** generalize this for other instructions
// *** initially, wfi is nop // *** initially, wfi is nop

9
pipelined/src/privileged/privileged.sv
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@ -88,7 +88,7 @@ module privileged (
logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW; logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW;
logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW; logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW;
logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM; logic sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM;
logic IllegalCSRAccessM; logic IllegalCSRAccessM;
logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM; logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM;
logic IllegalFPUInstrM; logic IllegalFPUInstrM;
@ -122,7 +122,6 @@ module privileged (
TrappedSRETM = 1; TrappedSRETM = 1;
NextPrivilegeModeM = PrivilegeModeW; NextPrivilegeModeM = PrivilegeModeW;
end else NextPrivilegeModeM = {1'b0, STATUS_SPP}; end else NextPrivilegeModeM = {1'b0, STATUS_SPP};
else if (uretM) NextPrivilegeModeM = `U_MODE; // *** can this happen without N mode?
else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8) else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE)) if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE))
NextPrivilegeModeM = `S_MODE; NextPrivilegeModeM = `S_MODE;
@ -141,7 +140,7 @@ module privileged (
privdec pmd(.InstrM(InstrM[31:20]), privdec pmd(.InstrM(InstrM[31:20]),
.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM, .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM,
.PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM, .PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM,
.uretM, .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM); .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM);
/////////////////////////////////////////// ///////////////////////////////////////////
// Control and Status Registers // Control and Status Registers
@ -150,7 +149,7 @@ module privileged (
.FlushE, .FlushM, .FlushW, .FlushE, .FlushM, .FlushW,
.StallE, .StallM, .StallW, .StallE, .StallM, .StallW,
.InstrM, .PCM, .SrcAM, .InstrM, .PCM, .SrcAM,
.CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .uretM, .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM,
.TimerIntM, .ExtIntM, .SwIntM, .TimerIntM, .ExtIntM, .SwIntM,
.MTIME_CLINT, .MTIME_CLINT,
.InstrValidM, .FRegWriteM, .LoadStallD, .InstrValidM, .FRegWriteM, .LoadStallD,
@ -208,7 +207,7 @@ module privileged (
.BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
.LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
.LoadPageFaultM, .StoreAmoPageFaultM, .LoadPageFaultM, .StoreAmoPageFaultM,
.mretM, .sretM, .uretM, .mretM, .sretM,
.PrivilegeModeW, .NextPrivilegeModeM, .PrivilegeModeW, .NextPrivilegeModeM,
.MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW, .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW,
.MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW,

5
pipelined/src/privileged/trap.sv
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@ -38,7 +38,7 @@ module trap (
(* mark_debug = "true" *) input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM, (* mark_debug = "true" *) input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
(* mark_debug = "true" *) input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM, (* mark_debug = "true" *) input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM,
(* mark_debug = "true" *) input logic LoadPageFaultM, StoreAmoPageFaultM, (* mark_debug = "true" *) input logic LoadPageFaultM, StoreAmoPageFaultM,
(* mark_debug = "true" *) input logic mretM, sretM, uretM, (* mark_debug = "true" *) input logic mretM, sretM,
input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, input logic [1:0] PrivilegeModeW, NextPrivilegeModeM,
(* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, (* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
@ -85,7 +85,7 @@ module trap (
assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE); assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
assign UTrapM = TrapM & (NextPrivilegeModeM == `U_MODE) & `N_SUPPORTED; assign UTrapM = TrapM & (NextPrivilegeModeM == `U_MODE) & `N_SUPPORTED;
assign RetM = mretM | sretM | uretM; assign RetM = mretM | sretM;
always_comb always_comb
if (NextPrivilegeModeM == `U_MODE) PrivilegedTrapVector = UTVEC_REGW; if (NextPrivilegeModeM == `U_MODE) PrivilegedTrapVector = UTVEC_REGW;
@ -115,7 +115,6 @@ module trap (
always_comb always_comb
if (mretM) PrivilegedNextPCM = MEPC_REGW; if (mretM) PrivilegedNextPCM = MEPC_REGW;
else if (sretM) PrivilegedNextPCM = SEPC_REGW; else if (sretM) PrivilegedNextPCM = SEPC_REGW;
else if (uretM) PrivilegedNextPCM = UEPC_REGW;
else PrivilegedNextPCM = PrivilegedVectoredTrapVector; else PrivilegedNextPCM = PrivilegedVectoredTrapVector;
// Cause priority defined in table 3.7 of 20190608 privileged spec // Cause priority defined in table 3.7 of 20190608 privileged spec

1
pipelined/testbench/common/instrNameDecTB.sv
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@ -102,7 +102,6 @@ module instrNameDecTB(
10'b1101111_???: name = "JAL"; 10'b1101111_???: name = "JAL";
10'b1110011_000: if (imm == 0) name = "ECALL"; 10'b1110011_000: if (imm == 0) name = "ECALL";
else if (imm == 1) name = "EBREAK"; else if (imm == 1) name = "EBREAK";
else if (imm == 2) name = "URET";
else if (imm == 258) name = "SRET"; else if (imm == 258) name = "SRET";
else if (imm == 770) name = "MRET"; else if (imm == 770) name = "MRET";
else if (funct7 == 9) name = "SFENCE.VMA"; else if (funct7 == 9) name = "SFENCE.VMA";