diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index e59888596..2608062c7 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -42,7 +42,7 @@ module csr #(parameter input logic StallE, StallM, StallW, input logic [31:0] InstrM, input logic [`XLEN-1:0] PCM, SrcAM, - input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM, + input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, input logic TimerIntM, ExtIntM, SwIntM, input logic [63:0] MTIME_CLINT, input logic InstrValidM, FRegWriteM, LoadStallD, @@ -128,7 +128,7 @@ module csr #(parameter csrsr csrsr(.clk, .reset, .StallW, .WriteMSTATUSM, .WriteSSTATUSM, .WriteUSTATUSM, .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW, - .mretM, .sretM, .uretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM, + .mretM, .sretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM, .MSTATUS_REGW, .SSTATUS_REGW, .USTATUS_REGW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW, .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM); diff --git a/pipelined/src/privileged/csrsr.sv b/pipelined/src/privileged/csrsr.sv index 1ccf6c8db..d4db6ba1d 100644 --- a/pipelined/src/privileged/csrsr.sv +++ b/pipelined/src/privileged/csrsr.sv @@ -36,7 +36,7 @@ module csrsr ( input logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM, input logic TrapM, FRegWriteM, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, - input logic mretM, sretM, uretM, + input logic mretM, sretM, input logic WriteFRMM, WriteFFLAGSM, input logic [`XLEN-1:0] CSRWriteValM, output logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW, @@ -156,9 +156,6 @@ module csrsr ( STATUS_SPIE <= #1 `S_SUPPORTED; STATUS_SPP <= #1 0; // Privileged 4.1.1 STATUS_MPRV_INT <= #1 0; // per 20210108 draft spec - end else if (uretM) begin - STATUS_UIE <= #1 STATUS_UPIE; - STATUS_UPIE <= #1 `U_SUPPORTED; end else if (WriteMSTATUSM) begin STATUS_TSR_INT <= #1 CSRWriteValM[22]; STATUS_TW_INT <= #1 CSRWriteValM[21]; diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index d53d88b8a..749f13878 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -37,12 +37,11 @@ module privdec ( input logic [1:0] PrivilegeModeW, input logic STATUS_TSR, output logic IllegalInstrFaultM, - output logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM); + output logic sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM); logic IllegalPrivilegedInstrM; // xRET defined in Privileged Spect 3.2.2 - assign uretM = PrivilegedM & (InstrM[31:20] == 12'b000000000010) & `N_SUPPORTED; assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED & PrivilegeModeW[0] & ~STATUS_TSR; assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == `M_MODE); @@ -51,7 +50,7 @@ module privdec ( assign ebreakM = PrivilegedM & (InstrM[31:20] == 12'b000000000001); assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101); assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001); - assign IllegalPrivilegedInstrM = PrivilegedM & ~(uretM|sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM); + assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM); assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | TrappedSRETM; // *** generalize this for other instructions // *** initially, wfi is nop diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index a14e35ad7..8bb4c05f7 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -88,7 +88,7 @@ module privileged ( logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW; logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW; - logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM; + logic sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM; logic IllegalCSRAccessM; logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM; logic IllegalFPUInstrM; @@ -122,7 +122,6 @@ module privileged ( TrappedSRETM = 1; NextPrivilegeModeM = PrivilegeModeW; end else NextPrivilegeModeM = {1'b0, STATUS_SPP}; - else if (uretM) NextPrivilegeModeM = `U_MODE; // *** can this happen without N mode? else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8) if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE)) NextPrivilegeModeM = `S_MODE; @@ -141,7 +140,7 @@ module privileged ( privdec pmd(.InstrM(InstrM[31:20]), .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM, .PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM, - .uretM, .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM); + .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM); /////////////////////////////////////////// // Control and Status Registers @@ -150,7 +149,7 @@ module privileged ( .FlushE, .FlushM, .FlushW, .StallE, .StallM, .StallW, .InstrM, .PCM, .SrcAM, - .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .uretM, + .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .TimerIntM, .ExtIntM, .SwIntM, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, @@ -208,7 +207,7 @@ module privileged ( .BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM, .LoadPageFaultM, .StoreAmoPageFaultM, - .mretM, .sretM, .uretM, + .mretM, .sretM, .PrivilegeModeW, .NextPrivilegeModeM, .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index be38baafa..da80c8993 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -38,7 +38,7 @@ module trap ( (* mark_debug = "true" *) input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM, (* mark_debug = "true" *) input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM, (* mark_debug = "true" *) input logic LoadPageFaultM, StoreAmoPageFaultM, - (* mark_debug = "true" *) input logic mretM, sretM, uretM, + (* mark_debug = "true" *) input logic mretM, sretM, input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, (* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, @@ -85,7 +85,7 @@ module trap ( assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE); assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; assign UTrapM = TrapM & (NextPrivilegeModeM == `U_MODE) & `N_SUPPORTED; - assign RetM = mretM | sretM | uretM; + assign RetM = mretM | sretM; always_comb if (NextPrivilegeModeM == `U_MODE) PrivilegedTrapVector = UTVEC_REGW; @@ -115,7 +115,6 @@ module trap ( always_comb if (mretM) PrivilegedNextPCM = MEPC_REGW; else if (sretM) PrivilegedNextPCM = SEPC_REGW; - else if (uretM) PrivilegedNextPCM = UEPC_REGW; else PrivilegedNextPCM = PrivilegedVectoredTrapVector; // Cause priority defined in table 3.7 of 20190608 privileged spec diff --git a/pipelined/testbench/common/instrNameDecTB.sv b/pipelined/testbench/common/instrNameDecTB.sv index 7ed309764..f0aaba92d 100644 --- a/pipelined/testbench/common/instrNameDecTB.sv +++ b/pipelined/testbench/common/instrNameDecTB.sv @@ -102,7 +102,6 @@ module instrNameDecTB( 10'b1101111_???: name = "JAL"; 10'b1110011_000: if (imm == 0) name = "ECALL"; else if (imm == 1) name = "EBREAK"; - else if (imm == 2) name = "URET"; else if (imm == 258) name = "SRET"; else if (imm == 770) name = "MRET"; else if (funct7 == 9) name = "SFENCE.VMA";